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CDCR81 Datasheet(PDF) 8 Page - Texas Instruments |
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CDCR81 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 16 page CDCR81 DIRECT RAMBUS ™ CLOCK GENERATOR SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 state transition latency specifications (continued) PARAMETER FROM TO TEST CONDITIONS MIN TYP† MAX UNIT t(ON) Minimum time in normal mode (STOPB = 1) before re-entering CLKSTOP (STOPB = 0) Normal CLK stop 100 ms t(DISTLOCK) Time from when CLK/CLKB output is settled to when the phase error between SYNCLKN and PCLKM falls within t(ERR-PD) Un- locked Locked 5 ms PARAMETER MEASUREMENT INFORMATION 39 Ω, ±5% 68 Ω, ±5% 68 Ω, ±5% 10 pF 100 pF 39 Ω, ±5% 10 pF RT = 28 Ω RT = 28 Ω Figure 1. Test Load and Voltage Definitions (VO(STOP), VO(X), VO, VOH, VOL) CLK CLKB tc1 tc2 Cycle-to-cycle jitter = | tc1 – tc2| over 10000 consecutive cycles Figure 2. Cycle-to-Cycle Jitter CLK CLKB tc3 Cycle-to-cycle jitter = | tc3 – tc4| over 10000 consecutive cycles tc4 Figure 3. Short Term Cycle-to-Cycle Jitter over 4 Cycles |
Similar Part No. - CDCR81_08 |
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