CDCR61A

DIRECT RAMBUS

™ CLOCK GENERATOR – LITE

SCAS626 – FEBRUARY 2000

7

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

CLK

CLKB

tpW+

t(cycle)

Duty cycle (tDC) = (tpW+/t(cycle))

Figure 5. Output Duty Cycle

CLK

CLKB

tpW+(i)

t(cycle)

Duty cycle error (tDC,ERR) = tpW+(i) – tpW+(i+1)

tpW+(i+1)

t(cycle)

Figure 6. Duty Cycle Error (Cycle-to-Cycle)

CLK

CLKB

VO(X)+

VO(X), nom

VO(X)–

Figure 7. Crossing-Point Voltage

LCLK

10 pF

1.8 V

120

Ω

120

Ω

80%

tf

tr

20%

VOL

VOH

Figure 8. LCLK Test Load Circuit and Voltage Waveform for CLK/CLKB and LCLK