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DP84910VHG-50 Datasheet(PDF) 6 Page - Texas Instruments

Part # DP84910VHG-50
Description  DP84910 DP84910-36 DP84910-50 Integrated Read Channel
Download  34 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP84910VHG-50 Datasheet(HTML) 6 Page - Texas Instruments

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Pin Definitions (Continued)
Pin
Description
POWER SUPPLY AND GROUND PINS
(Continued)
65
PULSE DETECTOR ANALOG SUPPLY VOLTAGE (PAVCC)
5V a5 b10%
66
PULSE DETECTOR ANALOG GROUND (PAGND)
68
FILTER ANALOG SUPPLY VOLTAGE (FVCC)
5V a5 b10%
69
FILTER ANALOG GROUND (FGND)
72
SYNCHRONIZER PLL ANALOG SUPPLY VOLTAGE (SYCVCC)
5V a5 b10%
75
SYNCHRONIZER PLL ANALOG GROUND (SYCGND)
78
SYNTHESIZER PLL ANALOG SUPPLY VOLTAGE (STHVCC)
5V a5 b10%
80
SYNTHESIZER PLL ANALOG GROUND (STHGND)
TTL LEVEL LOGIC PINS
1
WRITE GATE INPUT (WG)
This pin receives the write mode control input signal from the controller The logic polarity
for WG assertion is selectable via a bit in the control register (INV
WG Bank (11) bit 5) WG is active low if the control
register bit is set to invert (INV
WG e 1) When WG is active the pulse detector inputs (AMPIN1 and AMPIN2) are
held in a low impedance state and the automatic gain control of the puIse detector is in the hold mode There are no
setup or hold timing restrictions on WG enabling or disabling
2
IDLESERVO BAR POWER DOWN INPUT (IDLESERVO)
This input controls the power status of the servo detection
circuitry in the pulse detector When high (idle mode) this pin powers down all pulse detector circuitry except for biasing
circuitry necessary for quick recovery (k 15 ms) from this mode When low (servo mode) this pin powers on the circuitry
necessary for servo information detection in the puIse detector The synchronizer and synthesizer power are unaffected
by this pin The controI register power is also unaffected by the IDLESERVO pin but its input buffers are The control
register’s input’s are only powered on when the IDLESERVO pin is low Thus the controI register cannot be loaded
when the IDLESERVO pin is high The contents of the controI register is not affected by the state of the IDLESERVO
pin
3
SLEEP BAR POWER DOWN INPUT (SLEEP)
This active low input powers down aIl circuitry on the chip The control
register is powered down in this mode thus it does not retain its information The control register wiII be reset to the
initial power-on conditions when exiting the sleep mode The maximum supply current in the sleep mode is 2 mA
4
CONTROL REGISTER LATCHSHIFT BAR INPUT (CRLS)
A logical low on this input allows the CONTROL
REGISTER CLOCK input to shift data into the control register’s shift register via the CONTROL REGISTER DATA input
A positive transition latches the data into the addressed bank of latches and issues the information to the appropriate
circuitry within the device To minimize power consumption this pin should be kept at a logical high state except when
shifting data into the control register The SLEEP and IDLESERVO pins must be disabled (SLEEP e high and
IDLESERVO e low) in order to shift data into the control register
5
CONTROL REGISTER DATA INPUT (CRD)
ControI register data input
6
CONTROL REGISTER CLOCK INPUT (CRC)
Positive-edge-active control register clock input
7
FREQUENCY LOCK CONTROL BAR INPUT (FLC)
This input enables or disables the frequency lock function during a
read operation It has no effect when READ GATE is disabled Frequency lock is automatically employed for the full
duration of the time READ GATE is disabled regardless of the level of this input When READ GATE is taken to a logical
high level while FLC is at a logical low level (frequency lock enabled) the PLL is forced to lock to the pattern frequency
(2T or 3T sync field) selected in the control register (PREAM
2T Bank (11) bit 4) When FLC is taken to a logical high
level the frequency lock action is terminated and the PLL employs a pulse gate to accommodate random disk data
patterns There are no setup or hold timing restrictions on the positive-going transition of FLC
8
PREAMBLE DETECTED OUTPUT (PDT)
This output issues a logical high state after the following sequence the
enabling of READ GATE the completion of the zero-phase-start sequence and the detection of approximately 16
sequential pulses of 2T or 3T preamble Following preamble detection this output remains latched high until READ
GATE is disabled This output will be at a logical low state whenever READ GATE is inactive (low)
9
READ GATE INPUT (RG)
This input receives the read mode control input signal from the controller active high for a
read operation There are no setup or hold timing restrictions on RG enabling or disabling
10
DELAY LINE OUTPUT (DLO)
This active low open collector output pin issues encoded read data (ERD) delayed by
the selected value in the delay line at the input to the synchronizing latch By viewing this signal’s phase the user can
directly view the amount of window movement as the control register’s strobe bits are changed
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5


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