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BQ29312PWR Datasheet(PDF) 4 Page - Texas Instruments |
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BQ29312PWR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 39 page  www.ti.com ELECTRICAL CHARACTERISTICS bq29312 SLUS546E – MARCH 2003 – REVISED MARCH 2005 T A = 25°C, C(REG) = 4.7 µF, BAT = 14 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT No load at REG, TOUT, XALERT, SCLK, and SDATA. 60 90 ICC1 Supply current 1 ZVCHG = off ,VMEN = on, WDI no clock, µA TA = –25°C to 85°C 100 Select VC5 = VC4 = 0 V Supply current 2 No load at REG, TOUT, XALERT, SCLK, and SDATA. ICC2 (Depends of VM TA = –25°C to 85°C 25 50 µA ZVCHG = off, VMEN = off, WDI no clock topology selected) No load at REG, TOUT, XALERT, SCLK, and I(SLEEP) Sleep current SDATA.CHG, DSG and ZVCHG = off, REG = on, TA = –25°C to 85°C 20 40 µA VMEN = off, WDI no clock, SLEEP = REG or OPEN REG, CHG, DSG and ZVCHG = off, REG = off, I(SHIP) Ship current TA = –25°C to 85°C 0.1 1.0 µA VMEN = off, WDI no clock, VPACK= 0 V 3.3 V LDO 8.0 V < BAT or PACK ≤ 25 V, I O ≤ 25 mA –4% 3.3 2% V 6.5 V < BAT or PACK ≤ 8 V, I O ≤ 25 mA –9% 3.3 2% Regulator output V(REG) TA = –25°C to 85°C voltage 5.4 V ≤ BATor PACK ≤ 6.5 V, I O ≤ 16 mA –9% 3.3 2% V 4.5 V ≤ BAT or PACK ≤ 25 V, I O ≤ 2 mA –2% 3.3 2% V Regulator output ∆V (EGTEMP) change with 5.4 V ≤ BAT ≤ 25 V, I O = 2 mA, TA = –25°C to 85°C ±0.2% temperature ∆V (REGLINE) Line regulation 5.4 V ≤ BAT or PACK ≤ 25 V, I O = 2 mA 3 10 mV BAT = 14 V, 0.2 mA ≤ I O ≤ 2 mA 7 15 ∆V (REGLOAD) Load regulation mV BAT = 14 V, 0.2 mA ≤ I O ≤ 25 mA 40 100 BAT = 14 V, REG = 3.0 V 25 100 IMAX Current limit mA BAT = 14 V, REG = 0 V 12 50 CELL VOLTAGE MONITOR V(Cn) – V(Cn + 1) = 0 V, 8.0 V ≤ BAT or PACK ≤ 25 V 0.975 V(CELL OUT) CELL output V V(Cn) – V(Cn + 1) = 4.5 V, 8.0 V ≤ BAT or PACK ≤ 25 V 0.3 REF CELL output Mode(1), 8.0 V ≤ BAT or PACK ≤ 25 V –1% 0.975 1% V PACK/ PACK CELL output Mode(2) –5% 5% V 25 K = (CELL output (VC5 = 0.0 V, VC4 = 4.5 V) 0.147 0.150 0.153 – CELL output (VC5 = VC4 = 0.0 V)/ 4.5 K CELL scale factor K = (CELL output (VC2 = 13.5 V, VC1 = 18.0 V) 0.147 0.150 0.153 – CELL output (VC2 = VC1 = 13.5 V)/ 4.5 CELL output offset CELL output (VC2 = 17.0 V, VC1 = 17.0 V) VICR –1 mV error CELL output (VC2 = VC1 = 0.0 V) Cell balance internal R(BAL) rds(ON) for internal FET switch at VDS = 2.0 V 200 400 800 Ω resistance (1) Register Address =0x04, b2(CAL0) = b3(CAL1) = 1, Register Address = 0x03, b0(VMEN) = 1 (2) Register Address = 0x03, b1(PACKOUT) = 1, b0( VMEN) = 1 4 |
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