BQ3285S-SB2TR datasheet(2/26 Pages) TI1

Part #	BQ3285S-SB2TR

Description	Real-Time Clock (RTC)

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Block Diagram

Pin Descriptions

MOT

Bus type select input

MOT selects bus timing for either Motorola

or Intel architecture.

This pin should be

tied to VCC for Motorola timing or to VSS for

Intel timing (see Table 1).

The setting

should not be changed during system opera-

tion.

MOT is internally pulled low by a

30K

Ω resistor.

AD0–AD7

Multiplexed address/data input/

output

The bq3285 bus cycle consists of two

phases: the address phase and the data-

transfer phase.

The address phase pre-

cedes the data-transfer phase. During the

address phase, an address placed on

AD0–AD7 is latched into the bq3285 on the

falling edge of the AS signal. During the

data-transfer phase of the bus cycle, the

AD0–AD7 pins serve as a bidirectional data

bus.

AS

Address strobe input

AS serves to demultiplex the address/data

bus. The falling edge of AS latches the ad-

dress on AD0–AD7. This demultiplexing pro-

cess is independent of the CS signal.

For

DIP

and SOIC packages with MOT =

VCC, the AS input is provided a signal simi-

lar to ALE in an Intel-based system.

2

Bus

Type

MOT

Level

DS

Equivalent

R/W

Equivalent

AS

Equivalent

Motorola

VCC

DS,E,or

Φ2

R/W

AS

Intel

VSS

RD,

MEMR,or

I/OR

WR,

MEMW,or

I/OW

ALE

Table 1. Bus Setup

bq3285

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