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BQ4015MA-70 Datasheet(PDF) 7 Page - Texas Instruments |
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BQ4015MA-70 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 15 page Previous Data Valid Data Valid Address DOUT tRC tAA tOH High−Z High−Z CE DOUT tRC tACE tCLZ tCHZ bq4015/Y/LY www.ti.com SLUS125B – MAY 1999 – REVISED JANUARY 2010 Table 5. READ CYCLE (TA = TOPR, VCC(min) ≤ VCC ≤ VCC(max)) -70 -85 PARAMETER TEST CONDITIONS UNIT MIN MAX MIN MAX tRC Read cycle time 70 85 tAA Address access time 70 85 tACE Chip enable access time Output load A 70 85 tOE Output enable to output valid 35 45 tCLZ Chip enable to output in low Z 5 5 ns tOLZ Output enable to output in low Z 0 0 Output load B tCHZ Chip disable to output in high Z 0 25 0 35 tOHZ Output disable to output in high Z 0 25 0 25 tOH Output hold from address change Output load A 10 10 (1) WE is held high for a read cycle. (2) Device is continuously selected: CE = OE = VIL. Figure 5. Read Cycle No. 1 (Address Access) (1) WE is held high for a read cycle. (2) Device is continuously selected: CE = OE = VIL. (3) Address is valid prior to or coincident with CE transition low. Figure 6. Read Cycle No. 2 (CE Access) Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): bq4015/Y/LY Not Recommended For New Designs |
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