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BQ4285LSTR Datasheet(PDF) 8 Page - Texas Instruments |
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BQ4285LSTR Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 31 page  Power-Down/Power-Up Cycle The bq4285E/L power-up/power-down cycles are differ- ent. The bq4285L continuously monitors VCC for out-of- tolerance. During a power failure, when VCC falls below VPFD (2.53V typical), the bq4285L write-protects the clock and storage registers. The power source is switched to BC when VCC is less than VPFD and BC is greater than VPFD, or when VCC is less than VBC and VBC is less than VPFD. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VPFD, the power source is VCC. Write-protection continues for tCSR time af- ter VCC rises above VPFD. The bq4285E continuously monitors VCC for out-of- tolerance. During a power failure, when VCC falls below VPFD (4.17V typical), the bq4285E write-protects the clock and storage registers. When VCC is below VBC (3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VBC, the power source is VCC. Write- protection continues for tCSR time after VCC rises above VPFD. An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq4285E/L. As the voltage input VCC slows down during a power failure, the chip enable output, CEOUT, is forced inactive independent of the chip enable input CEIN. This activity unconditionally write-protects the external SRAM as VCC falls below VPFD. If a memory access is in process to the external SRAM during power-fail detec- tion, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time tWPT (30 µs maximum), the chip enable output is unconditionally driven high, write-protecting the controlled SRAM. As the supply continues to fall past VPFD, an internal switching device forces VOUT to the external backup energy source. CEOUT is held high by the VOUT energy source. During power-up, VOUT is switched back to the main supply as VCC rises above the backup cell input voltage sourcing VOUT.If VPFD <VBC on the bq4285L, the switch to the main supply occurs at VPFD.CEOUT is held inactive for time tCER (200ms maximum) after the power supply has reached VPFD, independent of the CEIN in- put, to allow for processor stabilization. During power-valid operation, the CEIN input is passed through to the CEOUT output with a propagation delay of less than 10ns. Figure 4 shows the hardware hookup for the external RAM. A primary backup energy source input is provided on the bq4285E/L. The BC input accepts a 3V primary bat- tery, typically some type of lithium chemistry. To pre- vent battery drain when there is no valid data to retain, VOUT and CEOUT are internally isolated from BC by the initial connection of a battery. Following the first appli- cation of VCC above VPFD, this isolation is broken, and the backup cell provides power to VOUT and CEOUT for the external SRAM. 8 bq4285E/L Figure 4. External RAM Hookup to the bq4285E/L RTC |
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