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AD9882KST-140 Datasheet(PDF) 10 Page - Analog Devices |
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AD9882KST-140 Datasheet(HTML) 10 Page - Analog Devices |
10 / 36 page REV. A –10– AD9882 PIN FUNCTION DETAIL (ANALOG INTERFACE) INPUTS RAIN Analog Input for RED Channel GAIN Analog Input for GREEN Channel BAIN Analog Input for BLUE Channel High impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. For RGB, the three channels are identical and can be used for any colors, but colors are assigned for convenient reference. For proper 4:2:2 formatting in a YPbPr application, the Y must be connected to the GAIN input, the Pb must be connected to the BAIN input, and the Pr must be connected to the RAIN input. They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation. HSYNC Horizontal Sync Input This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by Serial Register Bit 10H, Bit 6 (Hsync Polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V. Electrostatic Discharge (ESD) protection diodes will conduct heavily if this pin is driven more than 0.5 V above the maximum tolerance voltage (3.3 V), or more than 0.5 V below ground. VSYNC Vertical Sync Input This is the input for vertical sync. SOGIN Sync-on-Green Input This input is provided to assist with processing signals with embedded sync, typically on the GREEN channel. The pin is connected to a high speed comparator with an internally gener- ated threshold, which is set by the value of register 0FH, Bits 7–3. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT. When not used, this input should be left uncon- nected. For more details on this function and how it should be configured, refer to the Sync- on-Green section. SOGOUT Sync-on-Green Slicer Output This pin can be programmed to produce either the output from the Sync-on-Green slicer com- parator or an unprocessed but delayed version of the Hsync input. See the Sync Processing Block Diagram, Figure 18, to view how this pin is connected. Note: The output from this pin is the composite SYNC without additional processing from the AD9882. FILT External Filter Connection For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node. REFBYPASS Internal Reference BYPASS Bypass for the internal 1.25 V band gap refer- ence. It should be connected to ground through a 0.1 mF capacitor. The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most AD9882 applica- tions. If higher accuracy is required, an external reference may be employed instead. MIDBYPASS Midscale Voltage Reference BYPASS Bypass for the internal midscale voltage refer- ence. It should be connected to ground through a 0.1 mF capacitor. The exact voltage varies with the gain setting of the RED channel. HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. The duration of Hsync can only be programmed on the analog interface, not the digital. DATACK Data Output Clock The data clock output signal is used to clock the output data and HSOUT into external logic. It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all moved so the timing relationship among the signals is maintained. VSOUT Vertical Sync Output The separated Vsync from a composite signal or a direct pass-through of the Vsync input. The polarity of this output can be controlled via Register 10H, Bit 2. The placement and duration in all modes is set by the graphics transmitter. |
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