Timing Test Circuit

20057708

ADCS7476/ADCS7477/ADCS7478 Timing Specifications

The following specifications apply for V

all other limits T

Symbol

Parameter

Conditions

Typical

Limits

Units

t

CONVERT

16xt

SCLK

t

QUIET

(Note 5)

50

ns (min)

t

1

Minimum CS Pulse Width

10

ns (min)

t

2

CS to SCLK Setup Time

10

ns (min)

t

3

Delay from CS Until SDATA

20

ns (max)

t

4

Data Access Time after SCLK Falling

Edge(Note 7)

V

40

ns (max)

V

20

ns (max)

t

5

SCLK Low Pulse Width

0.4 x

t

SCLK

ns (min)

t

6

SCLK High Pulse Width

0.4 x

t

SCLK

ns (min)

t

7

SCLK to Data Valid Hold Time

V

7

ns (min)

V

5

ns (min)

t

8

SCLK Falling Edge to SDATA High

Impedance (Note 8)

V

25

ns (max)

6

ns (min)

V

25

ns (max)

5

ns (min)

t

POWER-UP

Power-Up Time from Full

Power-Down

1µs

Note 5: Minimum Quiet Time Required Between Bus Relinquish and Start of Next Conversion

Note 6: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V.

Note 7: Measured with the load circuit shown above, and defined as the time taken by the output to cross 1.0V or 2.0V.

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