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CP3SP33 Datasheet(PDF) 4 Page - Texas Instruments |
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CP3SP33 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 407 page  CP3SP33 SNOSCW5 – MAY 2013 www.ti.com 18.1 Open-Drain Operation ............................ 111 24.6 Communication Options ........................... 232 18.2 Port Registers ..................................... 111 24.7 Audio Interface Registers ......................... 235 19 Bluetooth Controller ................................ 115 24.8 Usage Example ................................... 243 19.1 RF Interface ....................................... 115 25 I 2S Interface ........................................... 244 19.2 Serial Interface .................................... 118 25.1 Interrupts and DMA ............................... 246 19.3 LMX5251 Power-Up Sequence ................... 122 25.2 Data Alignment .................................... 247 19.4 LMX5252 Power-Up Sequence ................... 123 25.3 I2S Interface Registers ............................ 247 19.5 Bluetooth Sleep Mode ............................ 124 26 Dual CVSD/PCM Conversion Modules .......... 253 19.6 Bluetooth Global Registers ....................... 125 26.1 Operation .......................................... 254 19.7 Bluetooth Sequencer RAM ........................ 126 26.2 PCM Conversions ................................. 255 19.8 Bluetooth Shared Data RAM ...................... 126 26.3 CVSD Conversion ................................. 255 20 Telematics Codec .................................... 126 26.4 Fixed-Rate PCM-to-CVSD Conversion ........... 255 20.1 CODEC ADC ...................................... 127 26.5 Fixed-Rate CVSD-to-PCM Conversion ........... 256 20.2 CODEC DAC ...................................... 128 26.6 Free-Running Mode ............................... 256 20.3 Compensation Filter ............................... 128 26.7 Interrupt Generation ............................... 256 20.4 Reconstruction Filter .............................. 129 26.8 DMA Support ...................................... 257 20.5 Peripheral Bus Interface .......................... 129 26.9 CVSD/PCM Audio Data Flow ..................... 257 20.6 Freeze Mode ...................................... 130 26.10 Bus Bandwidth and Latency Considerations .... 262 20.7 Reset .............................................. 130 26.11 Freeze Mode ..................................... 262 20.8 DC Protection Monitor ............................ 131 26.12 CVSD/PCM Converter Registers ................ 263 20.9 Sidetone Injection ................................. 131 27 Dual/Quad UART ..................................... 267 20.10 Telematics Codec Register Set .................. 131 27.1 Functional Overview .............................. 267 20.11 Usage Notes ..................................... 144 27.2 UART Operation ................................... 268 20.12 Tuning the Compensation Filter ................. 145 27.3 UART Registers ................................... 274 20.13 Obtaining Maximum DAC SNR .................. 145 27.4 Baud Rate Calculations ........................... 281 21 USB Controller ....................................... 145 28 Dual Microwire/SPI Interfaces ..................... 286 21.1 Modes of Operation ............................... 146 28.1 Microwire Operation ............................... 286 21.2 USB Connector Interface .......................... 147 28.2 Master Mode ...................................... 288 21.3 USB Controller Register Set ...................... 148 28.3 Slave Mode ....................................... 290 22 Dual CAN Interfaces ................................. 166 28.4 Interrupt Support .................................. 290 22.1 Functional Description ............................ 167 28.5 DMA Support ...................................... 291 22.2 Basic CAN Concepts .............................. 169 28.6 Freeze Mode ...................................... 292 22.3 Message Transfer ................................. 182 28.7 Microwire Interface Registers ..................... 292 22.4 Acceptance Filtering ............................... 182 29 Dual ACCESS.bus Interfaces ...................... 295 22.5 Receive Structure ................................. 184 29.1 ACCESS.bus Protocol Overview .................. 295 22.6 Transmit Structure ................................. 189 29.2 ACB Functional Description ....................... 298 22.7 Interrupts .......................................... 192 29.3 Interrupt Support .................................. 303 22.8 Time Stamp Counter .............................. 194 29.4 SMA Support ...................................... 303 22.9 Memory Organization ............................. 194 29.5 ACCESS.bus Interface Registers ................. 303 22.10 CAN Controller Registers ........................ 195 29.6 Usage Notes ...................................... 309 22.11 System Start-Up and Multi-Input Wake-Up ...... 209 30 Real Time Clock ...................................... 310 22.12 Usage Notes ..................................... 213 30.1 Programming ...................................... 311 23 Analog-to-Digital Converter ....................... 213 30.2 Interrupt ........................................... 311 23.1 Funcational Description ........................... 214 30.3 Reset .............................................. 311 23.2 Operation in Low-Power Modes .................. 216 30.4 Real-Time Clock Interface Registers .............. 311 23.3 Freeze Mode ...................................... 216 31 Timing and Watchdog Module .................... 315 23.4 ADC Register Set ................................. 217 31.1 TWM Structure .................................... 315 24 Advanced Audio Interface ......................... 221 31.2 Timer to Operation ................................ 315 24.1 Audio Interface Signals ............................ 221 31.3 Watchdog Operation .............................. 316 24.2 Audio Interface Modes ............................ 222 31.4 TWM Registers .................................... 317 24.3 Bit Clock Generation .............................. 227 31.5 Watchdog Programming Procedure .............. 320 24.4 Frame Clock Generation .......................... 228 32 Dual Multi-Function Timers ........................ 321 24.5 Audio Interface Operation ......................... 228 32.1 Timer Structure .................................... 321 4 Contents Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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