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TPS53317RGBT Datasheet(PDF) 7 Page - Texas Instruments |
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TPS53317RGBT Datasheet(HTML) 7 Page - Texas Instruments |
7 / 35 page TPS53317 www.ti.com SLUSAK4D – JUNE 2011 – REVISED JULY 2015 Electrical Characteristics (continued) over recommended free-air temperature range, VV5IN = 5.0 V, PGND = GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PROTECTION: OVP, UVP, PGOOD, and THERMAL SHUTDOWN PGOOD deassert to lower Measured at the VOUT pin wrt/ VPGDLL 84% (PGOOD → Low) VREFIN VPGHYSHL PGOOD high hysteresis 8% PGOOD de-assert to higher Measured at the VOUT pin wrt/ VPGDLH 116% (PGOOD → Low) VREFIN VPGHYSHH PGOOD high hysteresis -8% Measured at the VIN pin with a 2- VINMINPG Minimum VIN voltage for valid PGOOD mA sink current on PGOOD pin. 0.9 1.3 1.5 V V5IN is grounded here.(2) Measured at the VOUT pin wrt/ VOVP OVP threshold 117% 120% 123% VREFIN Measured at the VOUT pin wrt/ VUVP UVP threshold VREFIN, device latches OFF, begins 65% 68% 71% soft-stop Latch off controller, attempt soft- THSD Thermal shutdown(1) 145 °C stop. Controller re-starts after THSD(hys) Thermal Shutdown hysteresis(1) 10 °C temperature has dropped DRIVERS: BOOT STRAP SWITCH RDSONBST Internal BST switch on-resistance IBST = 10 mA, TA = 25°C 10 Ω IBSTLK Internal BST switch leakage current VBST = 14 V, VSW = 7 V 1 µA TIMERS: ON-TIME, MINIMUM OFF-TIME, SS, AND I/O TIMINGS VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 210 MHz tONESHOTC PWM one-shot(1) ns VVIN = 5 V, VVOUT = 1.05 V, fSW = 310 600 kHz VVIN = 5 V, VVOUT = 1.05 V, fSW = 1 tMIN(off) Minimum OFF time MHz, DRVL on, 270 ns SW = PGND, VVOUT < VREFIN From VOUT ramp starting to VOUT tINT(SS) Soft-start time 1.6 ms =95%, default setting From VVREF = 2 V to VOUT is ready tINT(SSDLY) Internal soft-start delay time 260 µs to ramp up At external tracking, the time from tPGDDLY PGOOD startup delay time 8 ms VOUT is ready to ramp up tPGDPDLYH PGOOD high propagation delay time 50 mV over drive, rising edge 0.8 1 1.2 ms tPGDPDLYL PGOOD low propagation delay time 50 mV over drive, falling edge 10 µs Time from the VOUT pin out of tOVPDLY OVP delay time 10 µs +20% of REFIN to OVP fault Time from EN_INT going high to 2 undervoltage fault is ready tUVDLYEN Undervoltage fault enable delay ms External tracking from VOUT ramp 8 starts Time from the VOUT pin out of tUVPDLY UVP delay time 256 µs –32% of REFIN to UVP fault LOGIC PINS: I/O VOLTAGE AND CURRENT PGOOD low impedance, ISINK = 4 VPGDPD PGOOD pull-down voltage 0.3 V mA, VV5IN = 4.5 V PGOOD high impedance, forced to IPGDLKG PGOOD leakage current –1 0 1 µA 5.5 V VENH EN logic high EN, VCCP logic 2 V VENL EN logic low EN, VCCP logic 0.5 V IEN EN input current 1 µA (2) If V5IN is higher than 1.5 V, PGOOD is valid regardless of the voltage applied at VIN. This is based on bench testing. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS53317 |
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