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ADUC7021BCP62 Datasheet(PDF) 4 Page - Analog Devices |
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ADUC7021BCP62 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 80 page  ADuC702x Series Preliminary Technical Data Rev. PrB | Page 4 of 80 Parameter ADuC702x Unit Test Conditions/Comments ANALOG OUTPUTS Output Voltage Range_0 Ouput Voltage Range_1 Output Voltage Range_2 0 to DACREF 0 to 2.5V 0 to DACVDD V typ V typ V typ DACREF range: DACGND to DACVDD Output Impedance 10 Ω typ DAC AC CHARACTERISTICS Voltage Output Settling Time Voltage Output Settling Time Digital to Analog Glitch Energy 10 15 TBD µs typ µs typ nV-sec typ DAC Output buffered DAC Output unbuffered I LSB change at major carry COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis Response Time ±10 5 AGND to AVDD-1.2 7 5 10 1 10 mV nA typ Vmin/Vmax pF typ mV min mv max µs min µs max Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response time may be modified via the CMPRES bits in the CMPCON register TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC TBD -1.5 mV typ mV/°C typ Accuracy ±3 °C typ POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection 2.79 V Two selectable Trip Points 3.07 V Power Supply Trip Point Accuracy ±2.5 % max Of the selected nominal Trip Point Voltage Watchdog Timer (WDT)4 Timeout Period 0 TBD ms min ms max Flash/EE MEMORY Endurance10 10,000 Cycles min Data Retention11 30 Years min TJ = 55°C Digital Inputs Input Leakage Current Input Capacitance ±10 ±1 10 µA max µA typ pF typ All digital inputs including XTAL1 and XTAL2 Logic Inputs4 VINL, Input Low Voltage VINH, Input High Voltage 0.4 2.0 V max V min All Logic inputs including XTAL1 and XTAL2 Logic Outputs VOH, Output High Voltage IOVDD – 400mV V min ISOURCE = 1.6mA VOL, Output Low Voltage12 0.4 V max ISINK = 1.6mA MCU CLOCK RATE 355.5 45.5 kHz min MHz max 8 programmable core clock selections within this range STARTUP TIME At Power-On From Idle Mode From Power-Down Mode TBD TBD TBD Core Clock = TBD MHz Programmable Logic Array (PLA) Propagation Delay TBD ns typ From input pin to output pin |
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