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ADUM1100UR Datasheet(PDF) 2 Page - Analog Devices |
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ADUM1100UR Datasheet(HTML) 2 Page - Analog Devices |
2 / 16 page REV. E –2– ADuM1100–SPECIFICATIONS ELECTRICAL SPECIFICATIONS, 5 V OPERATION1 Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current IDD1(Q) 0.3 0.8 mA VI = 0 V or VDD1 Output Supply Current IDD2(Q) 0.01 0.06 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) IDD1(25) 2.2 3.5 mA 12.5 MHz Logic Signal Frequency (See TPC 1) Output Supply Current 2 (25 Mbps) IDD2(25) 0.5 1.0 mA 12.5 MHz Logic Signal Frequency (See TPC 2) Input Supply Current (100 Mbps) IDD1(100) 9.0 14 mA 50 MHz Logic Signal Frequency, (See TPC 1) ADuM1100BR/ADuM1100UR Only Output Supply Current 2 (100 Mbps) IDD2(100) 2.0 2.8 mA 50 MHz Logic Signal Frequency, (See TPC 2) ADuM1100BR/ADuM1100UR Only Input Current II –10 +0.01 +10 µA0 ≤ V IN ≤ V DD1 Logic High Output Voltage VOH VDD2 – 0.1 5.0 V IO = –20 µA, V I = VIH VDD2 – 0.8 4.6 V IO = –4 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 µA, V I = VIL 0.03 0.1 V IO = 400 µA, V I = VIL 0.3 0.8 V IO = 4 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width 3 PW 40 ns CL = 15 pF, CMOS Signal Levels Maximum Data Rate 4 25 Mbps CL = 15 pF, CMOS Signal Levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width 3 PW 6.7 10 ns CL = 15 pF, CMOS Signal Levels Maximum Data Rate 4 100 150 Mbps CL = 15 pF, CMOS Signal Levels For All Grades Propagation Delay Time tPHL 10.5 18 ns CL = 15 pF, CMOS Signal Levels to Logic Low Output 5, 6 (See TPC 3) Propagation Delay Time tPLH 10.5 18 ns CL = 15 pF, CMOS Signal Levels to Logic High Output 5, 6 (See TPC 3) Pulse Width Distortion |tPLH – tPHL| 6 PWD 0.5 2 ns CL = 15 pF, CMOS Signal Levels Change versus Temperature 7 3 ps/ °CC L = 15 pF, CMOS Signal Levels Propagation Delay Skew tPSK1 8ns CL = 15 pF, CMOS Signal Levels (Equal Temperature) 6, 8 Propagation Delay Skew tPSK2 6ns CL = 15 pF, CMOS Signal Levels (Equal Temperature, Supplies) 6, 8 Output Rise/Fall Time tR, tF 3ns CL = 15 pF, CMOS Signal Levels Common-Mode Transient Immunity |CML|, 25 35 kV/ µsV I = 0 or VDD1, VCM = 1000 V, at Logic Low/High Output 9 |CMH|Transient Magnitude = 800 V Input Dynamic Power CPD1 35 pF Dissipation Capacitance 10 Output Dynamic Power CPD2 8pF Dissipation Capacitance 10 See Notes on page 5. Specifications subject to change without notice. (4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25 C, VDD1 = VDD2 = 5 V.) |
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