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LM2754 Datasheet(PDF) 4 Page - Texas Instruments |
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LM2754 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page LM2754 SNVS463A – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com Electrical Characteristics (1) (2) Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating junction temperature range (-40°C to +125 °C). Unless otherwise noted, specifications apply to the LM2754 Typical Application Circuit (pg.1) with V(IN, INSW) = 3.6V, VEN = 1.8V, VT/F = 0V, VTX = 0V, VSEL = 0V, CIN = C1 = C2 = 2.2µF, COUT = 4.7µF. (3) Symbol Parameter Conditions Min Typ Max Units VSETx ISETx Pin Voltage RSETx = 20kΩ −3.5% 1.244 +3.5% V IDx/ISETx LED Current to Set Current IDx = 50mA to 100mA −7% 795 +7% mA/mA Ratio (4) IDx = 200mA −11.5% 820 +11.5% VHR Current Sink Headroom IDx = 200mA 550 mV Voltage (5) IDx = 50mA 150 VOUT Output Voltage 1x Mode, IDx = 0mA 4.7 V 1.5x Mode, IDx = 0mA 4.7 2x Mode, IDx = 0mA 5.1 ROUT Output Impedance 1x Mode 0.25 Ω 1.5x Mode 1.3 2x Mode 1.5 IQ Quiescent Supply Current 1x Mode, IDx = 0mA 0.7 mA 1.5x Mode, IDx = 0mA 3.4 2x Mode, IDx = 0mA 6.3 8 ISD Shutdown Supply Current VEN = 0V 0.1 1 µA fSW Switching Frequency 0.7 1 1.3 MHz VIH Logic Input High Input Pins: EN, T/F, TX, SEL 1.2 V VIL Logic Input Low Input Pins: EN, T/F, TX, SEL 0.4 IIH Logic Input High Current (6) V(EN, T/F, TX, SEL) = 1.8V 4 µA IIL Logic Input Low Current (6) V(EN, T/F, TX, SEL) = 0V 0.5 µA (1) All voltages are with respect to the potential at the GND pin. (2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm. (3) CIN, COUT, C1, C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics (4) IDx/ISETx Ratio was tested with the Charge Pump in a gain of 1x. (5) Headroom Voltage (VHR) is the voltage across the current sinks (VDx) at which the current falls to 95% of the nominal programmed current. VHR is measured from VDx to GND. If the headroom voltage requirement is not met, LED current regulation will be compromised. (6) There is a 500k Ω resistor connected internally between each logic pin (EN, T/F, TX, SEL) and GND. 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM2754 |
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