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SN65HVD1040SKGD3 Datasheet(PDF) 8 Page - Texas Instruments |
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SN65HVD1040SKGD3 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 26 page  SN65HVD1040-HT SLLSEA6D – DECEMBER 2011 – REVISED AUGUST 2012 www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) TJ = -55°C to 125°C TJ = -55°C to 175°C TJ = -55°C to 210°C PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX Positive- going input VIT+ 800 900 800 900 800 900 threshold voltage STB at 0 V, See Table 3 Negative- High-speed going input VIT– mode 500 650 500 650 500 650 threshold mV voltage Hysteresis Vhys voltage STB at VCC 100 125 70 125 70 125 (VIT+ – VIT–) Input Standby VIT threshold STB at VCC 500 1150 500 1300 400 1350 mode voltage VOH High-level output voltage IO = –2 mA, See Figure 7 4 4.6 4 4.6 4 4.6 V VOL Low-level output voltage IO = 2 mA, See Figure 7 0.2 0.4 0.2 0.5 0.2 0.55 V CANH or CANL = 5 V, VCC at 0 II(off) Power-off bus input current 5 15 30 μA V, TXD at 0 V Power-off RXD leakage IO(off) VCC at 0 V, RXD at 5 V 20 30 30 μA current Input capacitance to ground, TXD at 3 V, VI = 0.4 sin (4E6πt) CI 20 20 20 pF (CANH or CANL) + 2.5 V CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 10 10 10 pF RID Differential input resistance TXD at 3 V, STD at 0 V 30 80 30 80 30 80 k Ω Input resistance, (CANH or RIN TXD at 3 V, STD at 0 V 15 30 40 15 30 40 15 30 40 CANL) Input resistance matching RI(m) [1 – (RIN (CANH) / RIN (CANL))] x VCANH = VCANL –3% 0% 3% –5% 0% 5% –12% 0% 12% 100% RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditiions (unless otherwise noted) TJ = -55°C to 125°C TJ = -55°C to 175°C TJ = -55°C to 210°C PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX tpLH Propagation delay time, low- 60 100 130 60 100 200 60 100 200 to-high-level output tpHL Propagation delay time, high- STB at 0 V, TXD at 3 V, See 45 70 130 45 70 200 45 70 200 ns to-low-level output Figure 7 tr Output signal rise time 8 8 8 tf Output signal fall time 8 8 8 tBUS Dominant time required on bus for wake-up from STB at VCC Figure 12 0.7 5 1.0 5.1 1.45 5.25 μs standby(1) (1) The device under test shall not signal a wake-up condition with dominant pulses shorter than tBUS (min) and shall signal a wake-up condition with dominant pulses longer than tBUS (max). Dominant pulses with a length between tBUS (min) and tBUS (max) may lead to a wake-up. SPLIT-PIN CHARACTERISTICS over recommended operating conditiions (unless otherwise noted) TJ = -55°C to 125°C TJ = -55°C to 175°C TJ = -55°C to 210°C TEST PARAMETER UNIT CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX VO Output voltage –500 μA < IO < 0.28×VC 0.5×VC 0.3×VCC 0.5×VCC 0.7×VCC 0.28×VCC 0.5×VCC 0.7×VCC 0.7×VCC V 500 μA C C IO(st Standby mode leakage STB at 2 V, b) current –12 V ≤ VO ≤ 12 –5 5 –7 7 –15 15 μA V 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: SN65HVD1040-HT |
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