PC87393F datasheet(9/148 Pages) NSC

Part #	PC87393F

Description	100-Pin LPC SuperI/O Devices for Portable Applications

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Manufacturer	NSC [National Semiconductor (TI)]

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Table of Contents (Continued)

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6.3.5

MIDI Command Register (MCOM) ............................................................................ 103

6.3.6

MIDI Control Register (MCNTL) ................................................................................ 104

6.4

MIDI PORT BITMAP ................................................................................................................ 105

7.0

X-Bus Extension

7.1

OVERVIEW ............................................................................................................................. 106

7.2

IRQ ROUTING ......................................................................................................................... 106

7.3

X-BUS TRANSACTIONS ......................................................................................................... 106

7.3.1

Programmable I/O Range Chip Select ...................................................................... 107

7.3.2

LPC and FWH Address to X-Bus Address Translation ............................................. 107

7.3.3

Extended Read/Write Signal Mode ........................................................................... 108

7.3.4

Indirect Memory Read and Write Transaction ........................................................... 108

7.3.5

Normal Address Mode X-Bus Transactions .............................................................. 108

7.3.6

Latched Address Mode X-Bus Transactions ............................................................. 110

7.4

X-BUS CONFIGURATION REGISTERS ................................................................................. 112

7.4.1

X-Bus Register Map .................................................................................................. 112

7.4.2

X-Bus Configuration Register (XBCNF) .................................................................... 112

7.4.3

X-Bus Select 0 Configuration Register (XZCNF0) ..................................................... 114

7.4.4

X-Bus Select 1 Configuration Register (XZCNF1) ..................................................... 115

7.4.5

X-Bus PIRQx Input Registers (XIRQCA to XIRQCD) ................................................ 116

7.4.6

X-Bus Indirect Memory Address Register 0 (XIMA0) ................................................ 117

7.4.7

X-Bus Indirect Memory Address Register 1 (XIMA1) ................................................ 117

7.4.8

X-Bus Indirect Memory Address Register 2 (XIMA2) ................................................ 118

7.4.9

X-Bus Indirect Memory Address Register 3 (XIMA3) ................................................ 118

7.4.10

X-Bus Indirect Memory Data Register (XIMD) ........................................................... 118

7.5

USAGE HINTS ....................................................................................................................... 118

7.6

X-BUS EXTENSION BITMAP .................................................................................................. 120

8.0

Legacy Functional Blocks

8.1

FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 121

8.1.1

General Description ................................................................................................... 121

8.1.2

FDC Register Map ..................................................................................................... 121

8.1.3

FDC Bitmap Summary ............................................................................................... 122

8.2

PARALLEL PORT .................................................................................................................... 123

8.2.1

General Description ................................................................................................... 123

8.2.2

Parallel Port Register Map ......................................................................................... 123

8.2.3

Parallel Port Bitmap Summary .................................................................................. 124

8.3

UART FUNCTIONALITY (SP1 AND SP2) ............................................................................... 126

8.3.1

General Description ................................................................................................... 126

8.3.2

UART Mode Register Bank Overview ....................................................................... 126

8.3.3

SP1 and SP2 Register Maps for UART Functionality ................................................ 127

8.3.4

SP1 and SP2 Bitmap Summary for UART Functionality ........................................... 129

8.4

IR FUNCTIONALITY (SP2) ..................................................................................................... 131

8.4.1

General Description ................................................................................................... 131

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