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UPD720100AGM-8EY Datasheet(PDF) 1 Page - NEC |
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UPD720100AGM-8EY Datasheet(HTML) 1 Page - NEC |
1 / 32 page The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. MOS INTEGRATED CIRCUIT µµµµPD720100A USB2.0 HOST CONTROLLER Document No. S15535EJ2V0DS00 (2nd edition) Date Published October 2002 NS CP (K) Printed in Japan DATA SHEET The mark shows major revised points. © 2001 The µPD720100A complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720100A is integrated three host controller cores with PCI interface and USB2.0 transceivers into a single chip. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. µµµµPD720100A User’s Manual: S15534E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) • Compliant with Open Host Controller Interface Specification for USB Rev 1.0a • Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95 • PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling. • Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core • All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. • Configurable number of downstream facing ports (2 to 5) • 32-bit 33 MHz host interface compliant to PCI Specification release 2.2. • Supports PCI Mobile Design Guide Revision 1.1. • Supports PCI-Bus Power Management Interface Specification release 1.1. • PCI Bus bus-master access • System clock is generated by 30 MHz X’tal or 48 MHz clock input. • Operational registers direct-mapped to PCI memory space • Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation. • 3.3 V power supply, PCI signal pins have 5 V tolerant circuit. ORDERING INFORMATION Part Number Package µPD720100AGM-8ED 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AGM-8EY 160-pin plastic LQFP (Fine pitch) (24 × 24) µPD720100AS1-2C 176-pin plastic FBGA (15 × 15) |
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