www.ti.com

SERIALIZER SWITCHING CHARACTERISTICS

t

TCP

2

) 3

DESERIALIZER TIMING REQUIREMENTS FOR REFCLK

DESERIALIZER SWITCHING CHARACTERISTICS

SN65LV1021

SN65LV1212

SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LVDS low-to-high transition time

0.2

1

Figure 4

LVDS high-to-low transition time

0.25

1

1

0

Figure 7

6.5

4.5

DO± high-to-high impedance

2.5

5

state delay

DO± low-to-high impedance state

2.5

5

delay

Figure 8

ns

DO± high-impedance

2.5

10

state-to-high delay

DO± high-impedance state-to-low

2.7

10

delay

SYNC pulse duration

andFigure 10

Serializer PLL lock time

Serializer delay

Bus LVDS bit width

over recommended operating supply and temperature ranges (unless otherwise specified)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFCLK period

25

T

100

ns

REFCLK duty cycle

40%

50%

60%

REFCLK transition time

3

6

ns

Frequency tolerance

-100

+100

ppm

over recommended operating supply and temperature ranges (unless otherwise specified)

TEST

PARAMETER

PIN/FREQ

MIN

TYP

MAX

UNIT

CONDITIONS

Receiver out clock period

RCLK

25

100

See Figure 11

CMOS/TTL low-to-high transition

0.7

2.5

time

ns

See Figure 5

CMOS/TTL high-to-low transition

K, RCLK

1.1

2.5

time

10 MHz

Room temperature,

Deserializer delay, See Figure 12

3.3 V

40 MHz

ns

See Figure 13

RCLK

RCLK duty cycle

40%

50%

60%

High-to-high impedance state

6.7

8

delay

Low-to-high impedance state

4.6

8

delay

See Figure 14

ns

High-impedance state-to-high

LOCK

5.5

8

delay

High-impedance state-to-low

4.8

8

delay

9