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SN65LV1023ADBG4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN65LV1023ADBG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 29 page www.ti.com SYNC1 SYNC2 DEN A+ A- PLL 10 SN65LV1023A LVDS Timing / Control TCLK_R/F DIN Y+ Y- PLL SN65LV1224A Timing / Control Clock Recovery 10 DOUT REN REFCLK LOCK RCLK_R/F RCLK (10 MHz to 66 MHz) TCLK (10 MHz to 66 MHz) FUNCTIONAL DESCRIPTION Initialization Mode SN65LV1023A SN65LV1224A SLLS570D – JUNE 2003 – REVISED JANUARY 2005 BLOCK DIAGRAMS The SN65LV1023A and SN65LV1224A are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down mode, and high-impedance mode. The following sections describe each state of operation. Initialization of both devices must occur before data transmission can commence. Initialization refers to synchronization of the serializer and deserializer PLLs to local clocks. When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state, while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs remain in the high-impedance state, while the PLL locks to the TCLK. 2 Submit Documentation Feedback |
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