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SN65LV1023AMDBREP Datasheet(PDF) 7 Page - Texas Instruments

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Part # SN65LV1023AMDBREP
Description  10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN65LV1023AMDBREP Datasheet(HTML) 7 Page - Texas Instruments

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SN65LV1023A-EP
SN65LV1224B-EP
SGLS358 – SEPTEMBER 2006
TERMINAL FUNCTIONS
PIN
I/O
DESCRIPTION
DB PACKAGE
SERIALIZER
18, 20, 23, 25
AGND
Analog circuit ground (PLL and analog circuits)
17, 26
AVCC
Analog circuit power supply (PLL and analog circuits)
LVTTL logic input. Low puts the LVDS serial output into the high-impedance state.
19
DEN
High enables serial data output.
15, 16
DGND
Digital circuit ground
3–12
DIN0 – DIN9
Parallel LVTTL data inputs
21
DO
Inverting LVDS differential output
22
DO+
Noninverting LVDS differential output
27, 28
DVCC
Digital circuit power supply
LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs
24
PWRDN
into the high-impedance state, putting the device into a low-power mode.
LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of
the two pins is asserted high for 6 cycles of TCLK, the serializer initiates
SYNC1,
transmission of a minimum 1026 SYNC patterns. If after completion of the
1, 2
SYNC2
transmission of 1026 patterns SYNC continues to be asserted, then the
transmission continues until SYNC is driven low and if the time SYNC holds > 6
cycles, another 1026 SYNC pattern transmission initiates.
LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a
13
TCLK_R/F
TCLK rising-edge data strobe.
LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to
14
TCLK
66-MHz clock. TCLK strobes parallel data into the input latch and provides a
reference frequency to the PLL.
DESERIALIZER
1, 12, 13
AGND
Analog circuit ground (PLL and analog circuits)
4, 11
AVCC
Analog circuit power supply (PLL and analog circuits)
14, 20, 22
DGND
Digital circuit ground
21, 23
DVCC
Digital circuit power supply
LVTTL level output. LOCK goes low when the deserializer PLL locks onto the
10
LOCK
embedded clock edge.
LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a
high-impedance state, putting the device into a low-power mode. To initiate power
7
PWRDN
down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low,
the device is in the power down state.
LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an
2
RCLK_R/F
RCLK rising-edge data strobe.
9
RCLK
LVTTL level output recovered clock. Use RCLK to strobe ROUTx.
LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL
3
REFCLK
frequency.
LVTTL logic input. Low places ROUT0–ROUT9 and RCLK in the high-impedance
8
REN
state.
5
RI+
Serial data input. Noninverting LVDS differential input
6
RI
Serial data input. Inverting LVDS differential input
28–24, 19–15
ROUT0–ROUT9
Parallel LVTTL data outputs
7
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