rp

rn

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SN65LVCP1414

www.ti.com

SLLSEC5A – AUGUST 2012 – REVISED JANUARY 2014

Electrical Characteristics (VCC 2.5V ±5%, 3.3V ±5%) (continued)

over operating free-air temperature range, all parameters are referenced to package pins (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

CML OUTPUTS (OUT[3:0]_P, OUT[3:0]_N)

1200

Output linear dynamic range

600

Output offset voltage

10

Output common mode voltage

See Figure 5

V

K28.5 pattern at 14.2Gbps on all 4 channels,

Common mode output ripple

10

20

No interconnect loss, VOD = HIGH

K28.5 pattern at 14.2Gbps on all channels,

Differential path output ripple

20

No interconnect loss, VIN = 1200mVpp.

Change in steady-state common-

mode output voltage between logic

±10

mV

states

Input signal with 30ps rise time, 20% to 80%, See Figure 7

31

ps

Input signal with 30ps fall time, 20% to 80%, See Figure 7

32

ps

SDD22

Differential output return loss

100MHz to 7.1GHz

–15

dB

SCC22

Common-mode output return loss

100MHz to 7.1GHz

–5

dB

Low-to-high propagation delay

65

ps

See Figure 6

High-to-low propagation delay

65

ps

All outputs terminated with 100

Ω, See Figure 8

8

ps

All outputs terminated with 100

Ω

50

ps

Single ended on-chip termination to VCC, Outputs will be AC

Single ended output resistance

50

Ω

coupled

Output termination mismatch at 1MHz

5

%

Channel-to-channel isolation

Frequency at 7.1GHz

35

45

dB

10MHz to 7.1GHz, No other noise source present, VOD = LOW

400

µVRMS

10MHz to 7.1GHz, No other noise source present, VOD = HIGH

500

µVRMS

EQUALIZATION

At 7.1GHz input signal

Equalization Gain, EQ = MAX

15

17

dB

Input signal with 3.75 pre-cursor and measure it on the output

signal,

Vpre

Output pre-cursor pre-emphasis

3.75

dB

Refer Figure 9. Vpre = 20log(V3/V2)

Input signal with 12dB post-cursor and measure it on the output

signal,

Vpst

Output post-cursor pre-emphasis

12

dB

Refer Figure 9, Vpst = 20log(V1/V2)

Transmit Side application

Residual deterministic jitter at 10.3125

Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain =

DJ1

0.016

UIp-p

Gbps

Low and VOD = High, Trace Mode Test Channel -> 0”, See

Figure 11

Receive Side Application

Residual deterministic jitter at 10.3125

Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High

DJ2

0.11

UIp-p

Gbps

and DCGain = High, Trace Mode Test Channel -> 12” (9dB loss

at 5GHz), See Figure 10

Transmit Side Application

Residual deterministic jitter at 14.2

Tx launch Amplitude = 0.6Vpp, EQ=0, ACGain and DCgain =

DJ3

0.041

UIp-p

Gbps

Low and VOD = High, Trace Mode Test Channel -> 0”, See

Figure 11

Receive Side Application

Residual deterministic jitter at 14.2

Tx launch Amplitude = 0.6Vpp, EQ=7, ACGain and VOD = High

DJ4

0.13

UIp-p

Gbps

and DCGain = High, Trace Mode Test Channel -> 8” (9dB loss

at 7GHz), See Figure 10

(2)

Rise and Fall measurements include board and channel effects of the test environment, refer to Figure 10 and Figure 11.

(3)

(4)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(5)

All noise sources added.

Copyright © 2012–2014, Texas Instruments Incorporated

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