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DESCRIPTION

PACKAGE DISSIPATION RATINGS

ABSOLUTE MAXIMUM RATINGS

SN65MLVD128

SN65MLVD129

SLLS586 – MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M-LVDS translators/repeaters. Outputs comply with the

M-LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to

125 MHz. The driver outputs have been designed to support multipoint buses presenting loads as low as 30

Ω

and incorporates controlled transition times for backbone operation.

M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for

RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The

SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each

output signal.

Intended applications for these devices include transmission of clock signals from a central clock module, as well

as translation and buffering of data or control signals for transmission through a controlled impedance backplane

or cable.

ORDERING INFORMATION

PART NUMBER

INPUT/OUTPUT CHANNEL

PART MARKING

PACKAGE/CARRIER

SN65MLVD128DGG

1:8

MLVD128

48-Pin TSSOP/Tube

SM65MLVD128DGGR

1:8

MLVD128

48-Pin TSSOP/Tape and Reeled

SN65MLVD129DGG

Dual 1:4

MLVD129

48-Pin TSSOP/Tube

SM65MLVD129DGGR

Dual 1:4

MLVD129

48-Pin TSSOP/Tape and Reeled

PCB JEDEC

PACKAGE

STANDARD

POWER RATING

POWER RATING

48-DGG

1114.6 mW

9.7 mW/°C

533.1 mW

48-DGG

1824.5 mW

15.9 mW/°C

872.6 mw

(1)

This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.

(2)

In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.

(3)

In accordance with the High-K thermal metric definitions of EIA/JESD51-7.

SN65MLVD128, 129

–0.5 V to 4 V

Input voltage range

D, EN

–0.5 V to 4 V

Output voltage range

A or B

–1.8 V to 4 V

A, B

±9 kV

All pins

±4 kV

Electrostatic discharge

All pins

±1500 V

All pins

200 V

Continuous power dissipation

See Dissipation Rating Table

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-B.

(4)

Tested in accordance with JEDEC Standard 22, Test Method C101-A.

(5)

Tested in accordance with JEDEC Standard 22, Test Method A115-A.

2

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