 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DP8421V Datasheet(PDF) 3 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
DP8421V Datasheet(HTML) 3 Page - National Semiconductor (TI) |
|
|
3 / 60 page  10 Introduction The DP8420V21V22V DP84T22 are CMOS Dynamic RAM controllers that incorporate many advanced features which include address latches refresh counter refresh clock row column and refresh address multiplexer delay line refreshaccess arbitration logic and high capacitive drivers The programmable system interface allows any manufacturer’s microprocessor or bus to directly interface via the DP8420V21V22V DP84T22 to DRAM arrays up to 64 Mbytes in size After power up the user must first reset and program the DP8420V21V22V DP84T22 before accessing the DRAM The chip is programmed through the address bus Reset Due to the differences in power supplies an External (hard- ware) Reset must be performed before programming the chip Programming After resetting the chip the user can program the controller by either one of two methods Mode Load Only Program- ming or Chip Select Access Programming Initialization Period Once the DP8420V21V22V DP84T22 has been pro- grammed for the first time a 60 ms initialization period is entered During this time the DRC performs refreshes to the DRAM array so further warm up cycles are unnecessary The initialization period is entered only after the first pro- gramming after a reset Accessing Modes After resetting and programming the chip the DP8420V21V22V DP84T22 is ready to access the DRAM There are two modes of accessing with these con- trollers Mode 0 which indicates RAS synchronously and Mode 1 which indicates RAS asynchronously Refresh Modes The DP8420V21V22V DP84T22 have expanded refresh capabilities compared to previous DRAM controllers There are three modes of refreshing available Internal Automatic Refreshing Externally ControlledBurst Refreshing and Re- fresh RequestAcknowledge Refreshing Any of these modes can be used together or separately to achieve the desired results Refresh Types These controllers have three types of refreshing available Conventional Staggered and Error Scrubbing Any refresh control mode can be used with any type of refresh Wait Support The DP8420V21V22V DP84T22 have wait support avail- able as DTACK or WAIT Both are programmable DTACK Data Transfer ACKnowledge is useful for processors whose wait signal is active high WAIT is useful for those processors whose wait signal is active low The user can choose either at programming These signals are used by the on chip arbiter to insert wait states to guarantee the arbitration between accesses refreshes and precharge Both signals are independent of the access mode chosen and both signals can be dynamically delayed further through the WAITIN signal to the DP8420V21V22V DP84T22 Sequential Accesses (Static ColumnPage Mode) The DP8420V21V22V DP84T22 have address latches used to latch the bank row and column address inputs Once the address is latched a COLumn INCrement (COL- INC) feature can be used to increment the column address The address latches can also be programmed to be fall through COLINC can be used for Sequential Accesses of Static Column DRAMs Also COLINC in conjunction with ECAS inputs can be used for Sequential Accesses to Page Mode DRAMs RAS and CAS Configuration (Byte Writing) The RAS and CAS drivers can be configured to drive a one two or four bank memory array up to 32 bits in width The ECAS signals can then be used to select one of four CAS drivers for Byte Writing with no extra logic Memory Interleaving When configuring the DP8420V21V22V DP84T22 for more than one bank Memory Interleaving can be used By tying the low order address bits to the bank select lines B0 and B1 sequential back to back accesses will not be de- layed since these controllers have separate precharge counters per bank Address Pipelining The DP8420V21V22V DP84T22 are capable of perform- ing Address Pipelining In address pipelining the DRC will guarantee the column address hold time and switch the in- ternal multiplexor to place the row address on the address bus At this time another memory access to another bank can be initiated Dual Accessing The DP8422V DP84T22 have all the features previously mentioned and unlike the DP8420V21V the DP8422V DP84T22 have a second port to allow a second CPU to access the same memory array The DP8422V DP84T22 have four signals to support Dual Accessing these signals are AREQB ATACKB LOCK and GRANTB All arbitration for the two ports and refresh is done on chip by the control- ler through the insertion of wait states Since the DP8422V DP84T22 have only one input address bus the address lines must be multiplexed externally The signal GRANTB can be used for this purpose TRI-STATE Outputs The DP84T22 implements TRI-STATE outputs When the input OE is asserted the output buffers are enabled when OE is negated logic 1 the output buffers at TRI-STATE (high Z) Terminology The following explains the terminology used in this data sheet The terms negated and asserted are used Asserted refers to a ‘‘true’’ signal Thus ‘‘ECAS0 asserted’’ means the ECAS0 input is at a logic 0 The term ‘‘COLINC assert- ed’’ means the COLINC input is at a logic 1 The term negat- ed refers to a ‘‘false’’ signal Thus ‘‘ECAS0 negated’’ means the ECAS0 input is at a logic 1 The term ‘‘COLINC negated’’ means the input COLINC is at a logic 0 The table shown below clarifies this terminology Signal Action Logic Level Active High Asserted High Active High Negated Low Active Low Asserted Low Active Low Negated High 3 |
Similar Part No. - DP8421V |
|
Similar Description - DP8421V |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
