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SN65HVD35DR Datasheet(PDF) 10 Page - Texas Instruments |
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SN65HVD35DR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 42 page  SN65HVD30, SN65HVD31, SN65HVD32 SN65HVD33, SN65HVD34, SN65HVD35 SLLS665K – SEPTEMBER 2005 – REVISED OCTOBER 2015 www.ti.com Switching Characteristics: Driver (continued) over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT SN65HVD33 45 Propagation delay time, high-impedance- tPZH1 SN65HVD34 235 ns to-high-level output RL = 110 Ω, RE at 0 V, SN65HVD35 490 D = 3 V and S1 = Y, or D = 0 V and S1 = Z SN65HVD33 25 See Figure 22 Propagation delay time, high-level-to- tPHZ SN65HVD34 65 ns high-impedance output SN65HVD35 165 SN65HVD33 35 Propagation delay time, high-impedance- tPZL1 SN65HVD34 190 ns to-low-level output RL = 110 Ω, RE at 0 V, SN65HVD35 490 D = 3 V and S1 = Z, or D = 0 V and S1 = Y SN65HVD33 30 See Figure 23 Propagation delay time, low-level-to- tPLZ SN65HVD34 120 ns high-impedance output SN65HVD35 290 tPZH1, Driver enable delay with bus voltage offset VO= 2 V (Typ) 500 900 ns tPZL1 RL = 110 Ω, RE at 3 V, D = 3 V and S1 = Y, or tPZH2 Propagation delay time, standby-to-high-level output 4000 ns D = 0 V and S1 = Z See Figure 22 RL = 110 Ω, RE at 3 V, D = 3 V and S1 = Z, or tPZL2 Propagation delay time, standby-to-low-level output 4000 ns D = 0 V and S1 = Y See Figure 23 7.10 Switching Characteristics: Receiver over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT SN65HVD30, SN65HVD33 26 45 ns Propagation delay time, tPLH SN65HVD31, SN65HVD32, low-to-high-level output 47 70 ns SN65HVD34, SN65HVD35 SN65HVD30, SN65HVD33 29 45 ns Propagation delay time, tPHL SN65HVD31, SN65HVD32, high-to-low-level output 49 70 ns VID = –1.5 V to 1.5 V, SN65HVD34, SN65HVD35 CL = 15 pF, See Figure 25 SN65HVD30, SN65HVD33 7 ns tsk(p) Pulse skew (|tPHL – tPLH|) SN65HVD31, SN65HVD34, 10 ns SN65HVD32, SN65HVD35 tr Output signal rise time 5 ns tf Output signal fall time 6 ns tPHZ Output disable time from high level 20 ns DE at 3 V CL = 15 pF, tPZH1 Output enable time to high level 20 ns See Figure 26 tPZH2 Propagation delay time, standby-to-high-level output DE at 0 V 4000 ns tPLZ Output disable time from low level 20 ns DE at 3 V CL = 15 pF, tPZL1 Output enable time to low level 20 ns See Figure 27 tPZL2 Propagation delay time, standby-to-low-level output DE at 0 V 4000 ns (1) All typical values are at 25°C and with a 3.3-V supply. 10 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: SN65HVD30 SN65HVD31 SN65HVD32 SN65HVD33 SN65HVD34 SN65HVD35 |
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