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DP8440VLJ-40 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
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DP8440VLJ-40 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
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9 / 46 page  30 Signal Descriptions (Continued) 35 CLOCK INPUTS Pin Device (if not Input Description Name Applicable to All) Output CLK I SYSTEM CLOCK This input may be in the range of 500 kHz to 40 MHz This input is generally a constant frequency but it may be controlled externally to change frequencies for some arbitrary reason This input provides the clock to the internal state machine that arbitrates between accesses and refreshes This clock’s positive edges and negative edges are used to extend the DTACK signal This clock is also used as a reference for the RAS precharge time the RAS low during refresh time and CAS precharge time DELCLK I DELAY LINE CLOCK The clock input DELCLK may be in the range of 10 MHz to 40 MHz and should be a multiple of 2 to have the DP844041 switching characteristics hold If DELCLK is not one of the above frequencies the accuracy of the internal delay line will suffer This happens because the phase lock loop that generates the delay line assumes an input clock frequency multiple of 2 MHz For example if DELCLK input is 17 MHz and we choose to divide by 8 (program bits C0 – 3) this will produce 2125 MHz which is 625% off of 2 MHz Therefore the DP844041 delay line will produce delays that are shorter (faster delays) than intended If divide by 9 was chosen the delay line would produce longer delays (slower delays) than intended (189 MHz instead of 2 MHz) This clock is also divided to create the internal refresh clock 36 POWER SIGNALS AND CAPACITOR INPUT Pin Device (if not Input Description Name Applicable to All) Output VCC I POWER Supply Voltage GND I GROUND Supply Voltage Reference CAP I CAPACITOR This input is used by the internal PLL for stabilization The value of the ceramic capacitor should be 01 mF and it should be connected between this input and ground 9 |
Similar Part No. - DP8440VLJ-40 |
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Similar Description - DP8440VLJ-40 |
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