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DP8440VLJ-25 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DP8440VLJ-25 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 46 page  20 Functional Introduction Reset and Programming After the power up the DP844041 must be reset and programmed before it can be used to access the DRAM The chip is programmed through the address bus Initialization Period After programming the DP844041 enter a 60 ms initialization period During this time the DP844041 perform refreshes to the DRAM Further warm up cycles are unnecessary The user must wait until the initialization is over to access the memory Modes of Operation The DP844041 are synchronous DRAM controllers Every access is synchronized to the sys- tem clock The controllers can be programmed in Page Mode or Normal Mode Burst accesses are dynamically re- quested through the input BSTARQ Opening Access They involve a new row address Regard- less of the access mode programmed opening accesses behave in the same way ADS and CS initiate and qualify every access After asserting the ADS the DP844041 will assert RAS from the next rising edge of the CLK The DP844041 will hold the row address on the DRAM address bus and guarantee that the row address is held for the Row Address Hold Time (tRAH) programmed The DRAM control- ler will then switch the internal multiplexor to place the col- umn address on the DRAM address bus and assert CAS DTACK will wait the programmed number of wait states be- fore asserting to indicate the end of the access Normal Access If the controller is programmed in Normal Mode (B1 e 1) RAS will assert and negate after the pro- grammed RAS low time The user can perform burst access if desired Page Access The DP844041 have an internal page com- parator This feature enables the user to do a series of ac- cesses without negating RAS for as long as the row address remains unchanged The user needs to provide a new ad- dress for every access The page comparator can also be programmed as an input This is beneficial for CPUs that have an internal page comparator The user can do burst accesses while in page if desired Burst Access These controllers can also generate new addresses to burst a specific number of locations The user can choose to burst in a wrap around fashion for 2 4 8 16 locations Or if the input NoWRAP is asserted the control- ler will burst consecutive locations and the column address will not wrap around The controller must be programmed in Latch Mode to generate the burst addresses Refresh Modes The DP844041 can perform Automatic Internal Refreshes or Externally Controlled Refreshes Dur- ing a long page access the controller can queue up to six refresh requests and burst refresh the addresses missed when the access finishes Refresh Types The DP844041 can be programmed to do all RAS Refresh Staggered Refresh Error Scrubbing during Refresh or CAS-before-RAS refresh Wait Support These controllers provide wait logic for all three types of accesses The user needs to program the desired number of wait states for opening page and burst accesses RAS and CAS Configurations The RAS outputs can be programmed to drive one two or four banks of memory and the CAS drivers can be programmed for byte writing in bus- es up to 64 bits wide TRI-STATE Outputs and Multiporting The GRANT input can be used for multi-porting When high this input will TRI-STATE the outputs allowing another controller to drive the DRAM Other Features Independent RAS precharge counters al- low memory interleaving thus back to back access to differ- ent memory banks is not delayed due to precharge The output NADTACK can be used to pipeline one address getting the next access to start one clock early The input NoWRAP will increment the address during a burst access in a linear fashion This is convenient for graphics or long page access Terminology This paragraph explains the terminology used in this data sheet The terms negated and asserted are used For example ECAS0 asserted means the ECAS0 in- put is at logic 0 The term NoWRAP asserted means that NoWRAP is at logic 1 6 |
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Similar Description - DP8440VLJ-25 |
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