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K6X1008T2D-GQ70 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6X1008T2D-GQ70 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 9 page CMOS SRAM K6X1008T2D Family Revision 1.0 September 2003 5 AC CHARACTERISTICS (VCC=2.7~3.6V, Commercial product:TA=0 to 70 °C, Industrial product:TA=-40 to 85°C, Automotive product:TA=-40 to 125°C ) 1. Voltage range is 3.0V~3.6V for commercial and industrial product. Parameter List Symbol Speed Bins Units 55ns1) 70ns 85ns Min Max Min Max Min Max Read Read Cycle Time tRC 55 - 70 - 85 - ns Address Access Time tAA - 55 - 70 - 85 ns Chip Select to Output tCO - 55 - 70 - 85 ns Output Enable to Valid Output tOE - 25 - 35 - 40 ns Chip Select to Low-Z Output tLZ 10 - 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 25 0 25 0 25 ns Output Disable to High-Z Output tOHZ 0 25 0 25 0 25 ns Output Hold from Address Change tOH 10 - 10 - 15 - ns Write Write Cycle Time tWC 55 - 70 - 85 - ns Chip Select to End of Write tCW 45 - 60 - 70 - ns Address Set-up Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 45 - 60 - 70 - ns Write Pulse Width tWP 40 - 50 - 60 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 25 0 25 0 30 ns Data to Write Time Overlap tDW 20 - 25 - 35 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - 5 - ns CL1) 1. Including scope and jig capacitance AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL DATA RETENTION CHARACTERISTICS 1. CS1 ≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V Item Symbol Test Condition Min Typ Max Unit Vcc for data retention VDR CS1 ≥Vcc-0.2V1) 2.0 - 3.6 V Data retention current IDR Vcc=3.0V, CS1 ≥Vcc-0.2V1) K6X1008T2D-B - - 6 µA K6X1008T2D-F - - 6 µA K6X1008T2D-Q 10 µA Data retention set-up time tSDR See data retention waveform 0 - - ms Recovery time tRDR 5 - - |
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