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DP8464BN-2 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DP8464BN-2 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 26 page Application Information (Continued) Region 1 is the high resolution area characterized by a large spread between flux reversals and a definite return to base- line (no signal) between these peaks Pulses of this type are predominantly found in drives which use either thin film heads or plated media or in drives which utilize run length limited codes (like the 27 code) which spread the distance between flux reversals A Region 2 waveform will vary from a tendency to return to the baseline (called shouldering) to almost sinusoidal at the higher frequencies These pulses come from drives which use limited frequency codes (such as MFM) The pulses may contain shouldering on the outer tracks of the disk and be nearly sinusoidal on the inner tracks since the flux densi- ty increases towards the inner track Detecting pulse peaks of waveforms of such variable char- acteristics requires a means of separating both noise and shouldering-caused errors from the true peaks In the past mild shoulder-caused errors were blocked by self-gating cir- cuits (such as the ‘‘de-snaker’’) These circuits fail when shouldering is extensive hence the need for the DP8464B which includes a peak sensing circuit and an amplitude sen- sitive gating channel in parallel The main circuit blocks of the DP8464B are shown in Figure 2 The output from the readwrite amplifier is fed directly to the Amp Input of the DP8464B This is the input of a Gain Controlled Amplifier The amplifier’s output voltage is fed back via an external filter to an internal fullwave rectifier and compared against the external voltage on the VREF pin The AGC circuit adjusts the gain of the amplifier to make the peak-to-peak differential Gate Channel input voltage four times the DC voltage on VREF The peak detection is performed by feeding the output of the Gain Controlled Amplifier through an external filter to the differentiator The differentiator output changes state when the input pulse changes direction generally this will be at the peaks However if the signal exhibits shouldering (the tendency to return to the baseline) as seen in Region 1 and the upper part of Region 2 the differentiator will also respond to noise near the baseline To avoid this the signal is also fed to a gating channel which is used to define a level either side of the baseline This gating channel com- prises a differential comparator with hysteresis and a D flip- flop The hysteresis for this comparator is externally set via the Set Hysteresis pin In order to have valid data out the input amplitude must first cross the hysteresis level This will change the logic level on the D input of the flip-flop The peak of the input signal will generate a pulse out of the differentiator and bi-directional one shot This pulse will clock in the new data on the D input which will appear at the Q output In this way when the differentiator is respond- ing to noise at the baseline the output of the D flop is not changing since the logic level into the D input has not yet changed The comparator circuitry is therefore a gating channel to prevent any noise near the baseline from con- taminating the data The amount of hysteresis is twice the DC voltage on the Set Hysteresis pin For instance if the voltage on the Set Hys- teresis pin is 03V the differential Gate Channel Input must be larger than 06V (g03V) before the output of the com- parator will change states The Time Pulse Out Encoded Data and Channel Alignment Output are designed to drive 1 standard TTL gate TLF5283 – 5 TLF5283 – 6 FIGURE 1 Pulse Amplitude vs Bit Density with Typical Waveforms 7 |
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