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SN74LVC1G374YZPR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LVC1G374YZPR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 13 page SN74LVC1G374 SINGLE DTYPE FLIPFLOP WITH 3STATE OUTPUT SCES520A − DECEMBER 2003 − REVISED JUNE 2004 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUT OE CLK D OUTPUT Q L ↑ L L L ↑ HH L H or L X Q H X X Z logic diagram (positive logic) OE 6 1 3 4 CLK D C1 D Q |
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