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DP84902M Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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DP84902M Datasheet(HTML) 5 Page - National Semiconductor (TI) |
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5 / 16 page  Control Register Operating Conditions are guaranteed over operating conditions (see table) unless otherwise specified Symbol Parameter Min Typ Max Units Test (Note 1) tPW(CRC) CRC Pulse Width (positive or negative) (see Figures 4 and 9 ) 14 ns (Note A) tSU(CRD) CRD Setup Time with respect to CRC (positive edge) 5 ns (Note A) (see Figures 4 and 8 ) tH(CRD) CRD Hold Time with respect to CRC (positive edge) 5 ns (Note A) (see Figures 4 and 8 ) tSU(CRLS) CRLS Setup Time with respect to CRC (positive edge) 5 ns (Note A) (see Figures 4 and 8 ) tH(CRLS) CRLS Hold Time with respect to CRC (positive edge) 5 ns (Note A) (see Figures 4 and 8 ) Note 1 Typical values are specified at 25 C and 5V supply Note A This parameter is guaranteed by outgoing testing TLF11963 – 4 FIGURE 4 Control Register Timing Diagram 5 |
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