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DP8570AN Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DP8570AN Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 26 page  AC Electrical Characteristics VCC e 5V g10% VBB e 3V VPFAIL l VIH CL e 100 pF (unless otherwise specified) Symbol Parameter Min Max Units READ TIMING tAR Address Valid Prior to Read Strobe 20 ns tRW Read Strobe Width (Note 9) 80 ns tCD Chip Select to Data Valid Time 80 ns tRAH Address Hold after Read (Note 10) 3 ns tRD Read Strobe to Valid Data 70 ns tDZ Read or Chip Select to TRI-STATE 60 ns tRCH Chip Select Hold after Read Strobe 0 ns tDS Minimum Inactive Time between Read or Write Accesses 50 ns WRITE TIMING tAW Address Valid before Write Strobe 20 ns tWAH Address Hold after Write Strobe (Note 10) 3 ns tCW Chip Select to End of Write Strobe 90 ns tWW Write Strobe Width (Note 11) 80 ns tDW Data Valid to End of Write Strobe 50 ns tWDH Data Hold after Write Strobe (Note 10) 3 ns tWCH Chip Select Hold after Write Strobe 0 ns TIMER 0TIMER 1 TIMING FTCK Input Frequency Range DC 10 MHz tCK Propagation Delay Clock to Output 120 ns tGO Propagation Delay G0 to G1 100 ns to Timer Output (Note 12) O tPGW Pulse Width G0 or G1 (Note 12) 25 ns tGS Setup Time G0 G1 to TCK (Note 13) 100 ns INTERRUPT TIMING tROLL Clock Rollover to INTR Out is Typically 165 ms Note 9 Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low Hence read commences when both signals are low and terminates when either signal returns high Note 10 Hold time is guaranteed by design but not production tested This limit is not used to calculate outgoing quality levels Note 11 Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low Hence write commences when both signals are low and terminates when either signal returns high Note 12 Timers in Mode 3 Note 13 Guaranteed by design not production tested This limit is not used to calculate outgoing quality levels AC Test Conditions Input Pulse Levels GND to 30V Input Rise and Fall Times 6 ns (10% – 90%) Input and Output 13V Reference Levels TRI-STATE Reference Active High a05V Levels (Note 15) Active Low b05V Note 14 CL e 100 pF includes jig and scope capacitance Note 15 S1 e VCC for active low to high impedance measurements S1 e GND for active high to high impedance measurements S1 e open for all other timing measurements Capacitance (TA e 25 C f e 1 MHz) Symbol Parameter Typ Units (Note 16) CIN Input Capacitance 5 pF COUT Output Capacitance 7 pF Note 16 This parameter is not 100% tested Note 17 Output rise and fall times 25 ns max (10%–90%) with 100 pF load TLF8638 – 23 3 |
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