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STA310 Datasheet(PDF) 8 Page - STMicroelectronics |
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STA310 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 90 page  STA310 8/90 3.2 Functional diagram Figure 2. Audio decoder top level functional diagram 3.3 Control interface description The IC can be controlled either by a host using an I²C interface, or by a general purpose host interface. These interfaces provide the same functions and are described in the following sections. The selection is per- formed by the means of the pin SELI2C: when high, this pin indicates that the I²C interface is used. When low, the parallel interface is used. 3.3.1 Parallel control interface When the pin SELI2C is low, the control of the chip is performed through the parallel interface. When accessing the device through the parallel interface, the following signals are used: - The address bus A[7..0]. It is used to select one of the 256 register locations. - The data bus DATA[7..0]. If a read cycle is requested, the data lines D[7:0] will be driven by the IC. For a write cycle, the STA310 will latch the data placed on the data lines when the WAIT signal is driven high. - The signal R/W. It defines the type of register access: either read (when high), or write (when low). Some registers can be either written or read, some are read only, some are write only. - The signal DCSB. A cycle is defined by the assertion of the signal DCSB. Note: 1. The address bus A[7..0], and read/write signal R/W must be setup before the DCSB line is activated. PCMOUT1 PCMOUT3 STA310 LPCM PCM Sample Rate Converter PCMOUT0 Pink Noise Gen Beep Tone Gen L/Lt R/Rt C Lfe Ls Rs DELAY DELAY DELAY L R C lfe Ls Rs Downmix Lt/Rt LVCR RVCR I958OUT video NULL DATA IEC 1937 (AC-3 / MPEG 2) L R C lfe Ls Rs 2 6 PCMOUT2 2 to 6 ch 63 60 61 62 SIN2 LRCLKIN2 DSTRB2 REQ2 I2S_IN2 73 DELAY DELAY DELAY DELAY DELAY 76 77 72 63 SCLK 68 LRCLK 69 PCMCLK 31 CLK 64 CLKOUT System and Audio Clocks 58 Switctch PCM CDDA MPEG 1 Layer 1-2 2/0 2to2 6to2 Voice Effects: Echo, Chorus Reverb Gain Level Sensitive Cancel MP3 6 6 2 2 2 2 AC-3 STA310 6 1..4 1..6 CONTROL 53 46 43 48 21 D[0..7] A[0..7] MAINI2CADR SCLKI2C SDAI2C IRQ DCSB I2S_IN1 FRAME BUFFER 42 41 40 37 SIN LRCLKIN DSTRB REQ PACKET FORMATTER PTS MPEG 2 MLP |
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