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SN74ALVCH16823DGVR Datasheet(PDF) 1 Page - Texas Instruments

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Part # SN74ALVCH16823DGVR
Description  18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ALVCH16823DGVR Datasheet(HTML) 1 Page - Texas Instruments

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FEATURES
DESCRIPTION
DGG OR DL PACKAGE
(TOP VIEW)
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1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1CLK
1CLKEN
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2CLKEN
2CLK
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or
SN74ALVCH16823
18-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES038F – JULY 1995 – REVISED APRIL 2005
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
This 18-bit bus-interface flip-flop is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16823
features
3-state
outputs
designed specifically for driving highly capacitive or
relatively
low-impedance
loads.
This
device
is
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The SN74ALVCH16823 can be used as two 9-bit
flip-flops or one 18-bit flip-flop. With the clock-enable
(CLKEN) input low, the D-type flip-flops enter data on
the low-to-high transitions of the clock. Taking
CLKEN high disables the clock buffer, thus latching
the outputs. Taking the clear (CLR) input low causes
the Q outputs to go low independently of the clock.
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16823 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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