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TPS70802 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS70802 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 29 page TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PG2 timing diagram (assuming VIN1 already powered up) NOTE A: VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. t t t PG2 Output VIT+ (see Note A) VIN2 VOUT2 VIT – (see Note A) Threshold Voltage Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION EN1 5 I Active low enable for VOUT1 EN2 6 I Active low enable for VOUT2 GND 8 Ground MR 4 I Manual reset input, active low, pulled up internally NC 1, 11, 20 No connection PG1 16 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage PG2 15 O Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage RESET 7 I Open drain output, SVS (power on reset) signal, active low VIN1 2, 3 I Input voltage of regulator 1 VIN2 9, 10 I Input voltage of regulator 2 VOUT1 18, 19 O Output voltage of regulator 1 VOUT2 12, 13 O Output voltage of regulator 2 VSENSE2/FB2 14 I Regulator 2 output voltage sense/ regulator 2 feedback for adjustable VSENSE1/FB1 17 I Regulator 1 output voltage sense/ regulator 1 feedback for adjustable |
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