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DP8571 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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DP8571 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
11 / 24 page Functional Description (Continued) TLF9979 – 10 FIGURE 6 System-Battery Switchover (Upper Left) Power Fail and Lock-Out Circuits (Lower Right) The user may choose to have this power failed signal lock- out the TCP’s data bus within 30 ms min63 ms max or to delay the lock-out to enable mP access after power failure is detected This delay is enabled by setting the delay enable bit in the Routing Register Also if the lock-out delay was not enabled the TCP will disconnect itself from the bus with- in 30 ms min x 63 ms max If chip select is low when a power failure is detected a safety circuit will ensure that if a read or write is held active continuously for greater than 30 ms after the power fail signal is asserted the lock-out will be forced If a lock-out delay is enabled the DP8571A will remain active for 480 ms after power fail is detected This will enable the mP to perform last minute bookkeeping be- fore total system collapse When the host CPU is finished accessing the TCP it may force the bus lock-out before 480 ms has elapsed by resetting the delay enable bit The battery switch over circuitry is completely independent of the PFAIL pin A separate circuit compares VCC to the VBB voltage As the main supply fails the TCP will continue to operate from the VCC pin until VCC falls below the VBB voltage At this time the battery supply is switched in VCC is disconnected and the device is now in the standby mode If indeterminate operation of the battery switch over circuit is to be avoided then the voltage at the VCC pin must not be allowed to equal the voltage at the VBB pin After the generation of a lock-out signal and eventual switch in of the battery supply the pins of the TCP will be configured as shown in Table II Outputs that have a pull-up resistor should be connected to a voltage no greater than VBB TABLE II Pin Isolation during a Power Failure Pin PFAIL e Standby Mode Logic 0 VBB l VCC CS RD WR Locked Out Locked Out A0 – A4 Locked Out Locked Out D0 – D7 Locked Out Locked Out Oscillator Not Isolated Not Isolated PFAIL Not Isolated Not Isolated INTR MFO Not Isolated Open Drain The Timer and Interrupt Power Fail Operation bits in the Real-Time Mode Register determine whether or not the tim- ers and interrupts will continue to function after a power fail event As power returns to the system the battery switch over cir- cuit will switch back to VCC power as soon as it becomes greater than the battery voltage The chip will remain in the locked out state as long as PFAIL e 0 When PFAIL e 1 11 |
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Similar Description - DP8571 |
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