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74AUP1G126DRLRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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74AUP1G126DRLRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 29 page (1) Single, dual, and triple gates 3.3-V Logic (1) 3.3-V Logic (1) Switching Characteristics at 25 MHz (1) (1) AUP1G08 data at C = 15 pF L SN74AUP1G126 SCES596F – JULY 2004 – REVISED MAY 2010 www.ti.com Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION(1) ORDERABLE PART TOP-SIDE TA PACKAGE(2) NUMBER MARKING(3) NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G126YFPR _ _ _ HN _ 0.23-mm Large Bump – YFP NanoStar™ – WCSP (DSBGA) Reel of 3000 SN74AUP1G126YZPR _ _ _ HN _ 0.23-mm Large Bump – YZP (Pb-free) QFN – DRY Reel of 5000 SN74AUP1G126DRYR HN mQFN – DSF Reel of 5000 SN74AUP1G126DSFR HN –40°C to 85°C Reel of 3000 SN74AUP1G126DBVR SOT (SOT-23) – DBV H26_ Reel of 250 SN74AUP1G126DBVT Reel of 3000 SN74AUP1G126DCKR SOT (SC-70) – DCK HN_ Reel of 250 SN74AUP1G126DCKT SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G126DRLR HN_ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP/YZT: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT Y OE A H H H H L L L X(1) Z (1) Floating inputs allowed 2 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated Product Folder Link(s): SN74AUP1G126 |
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