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SP6120 Datasheet(PDF) 9 Page - Exar Corporation |
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SP6120 Datasheet(HTML) 9 Page - Exar Corporation |
9 / 22 page 9 Date: 1/21/05 SP6120 Low Voltage, AnyFETTM, Synchronous, Buck Controller © Copyright 2005 Sipex Corporation THEORY OF OPERATIONS: Continued driver as well as whether the controller is oper- ating in continuous or discontinuous mode. The Fault Logic holds the high and low side drivers off if VCC dips below 2.75V, if an over current condition exists, or if the part is disabled through the ENABLE pin. The Zero Crossing Compara- tor turns the lower driver off if the conduction current reaches zero and the Driver Logic has made an attempt to turn the lower driver on and the Programming Logic is set for discontinuous mode. Lastly, the 4 Ω drivers have internal gate non-overlap circuitry and are designed to drive MOSFETs associated with converter designs in the 5A to 10A range. Typically the high side driver is referenced to the SWN pin; further improving the efficiency and performance of the converter. ENABLE Low quiescent mode or “Sleep Mode” is initi- ated by pulling the ENABLE pin below 650mV. The ENABLE pin has an internal 4 µA pull-up current and does not require any external inter- face for normal operation. If the ENABLE pin is driven from a voltage source, the voltage must be above 1.45V in order to guarantee proper “awake” operation. Assuming that VCC is above 2.85V, the SP6120 transitions from “Sleep Mode” to “Awake Mode” in about 20 µs to 30µs and from “Awake Mode” to “Sleep Mode” in a few microseconds. SP6120 quiescent current in sleep mode is 20 µA maximum. During Sleep Mode, the high side and low side MOSFETs are turned off and the COMP and SS pins are held low. UVLO Assuming that the ENABLE pin is either pulled high or floating, the voltage on the VCC pin then determines operation of the SP6120. As VCC rises, the UVLO block monitors VCC and keeps the high side and low side MOSFETs off and the COMP and SS pins low until VCC reaches 2.85V. If no faults are present, the SP6120 will initiate a soft start when VCC exceeds 2.85V. Hysteresis (about 100mV) in the UVLO comparator pro- vides noise immunity at start-up. Soft Start (see figures on next page) Soft start is required on step-down controllers to prevent excess inrush current through the power train during start-up. Typically this is managed by sourcing a controlled current into a program- ming capacitor (on the SS pin) and then using the voltage across this capacitor to slowly ramp up either the error amp reference or the error amp output (COMP). The control loop creates narrow width driver pulses while the output voltage is low and allows these pulses to in- crease to their steady-state duty cycle as the output voltage increases to its regulated value. As a result of controlling the inductor volt*second product during start-up, inrush cur- rent is also controlled. The presence of the output capacitor creates extra current draw during start-up. Simply stated, dVOUT/dt requires an average sustained current in the output capacitor and this current must be considered while calculating peak inrush cur- rent and over current thresholds. Since the SP6120 Soft Start: (continued) ramps up the error amp reference voltage, an expression for the output capacitor current can be written as: ICOUT = (COUT/CSS) * (VOUT/1.25) * 50µA As the figure shows, the SS voltage controls a variety of signals. First, provided all the exter- nal fault conditions are removed, the fault latch is reset and the SS cap begins to charge. When the SS voltage reaches around 0.3V, the error amp reference begins to track the SS voltage while maintaining the 0.3V differential. As the SS voltage reaches 0.7V, the driver begins to switch the high side and low side MOSFETs with narrow pulses in an effort to keep the converter output regulated. As the error amp reference ramps upward, the driver pulses widen until a steady state value is reached. The “bump” in the inductor current transfer curve is indica- tive of excess charge current incurred due to the |
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