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PCI4520ZHK Datasheet(PDF) 1 Page - Texas Instruments |
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PCI4520ZHK Datasheet(HTML) 1 Page - Texas Instruments |
1 / 7 page www.ti.com FEATURES PCI4520 GHK/ZHK SLLA242 – JULY 2006 Dual-Socket PC Card and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller • Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity • PC Card Standard 8.0 compliant terminals • PCI Bus Power Management Interface • Fully interoperable with FireWire™ and Specification 1.1 compliant i.LINK™ implementations of IEEE Std 1394 • Advanced Configuration and Power Interface • Compliant with Intel Mobile Power Guideline Specification 2.0 compliant 2000 • PCI Local Bus Specification Revision 2.2 • Full IEEE Std 1394a-2000 support includes: compliant connection debounce, arbitrated short reset, • PC 98/99 and PC2001 compliant multispeed concatenation, arbitration • Compliant with the PCI Bus Interface acceleration, fly-by concatenation, and port Specification for PCI-to-CardBus Bridges disable/suspend/resume • Fully compliant with provisions of IEEE Std • Power-down features to conserve energy in 1394-1995 for a high-performance serial bus battery-powered applications include: and IEEE Std 1394a-2000 automatic device power down during • Fully compliant with 1394 Open Host suspend, PCI power management for Controller Interface Specification 1.1 link-layer and inactive ports powered down, • Compatible with TPS2228, TPS2226, ultralow-power sleep mode TPS2224, TPS2223, TPS2226A, TPS2224A, • Two IEEE Std 1394a-2000 fully compliant and TPS2223A PC Card power switches cable ports at 100M bits/s, 200M bits/s, and • 1.8-V core logic and 3.3-V I/O cells with 400M bits/s internal voltage regulator to generate 1.8-V • Cable ports monitor line conditions for active core VCC connection to remote node • Universal PCI interfaces compatible with • Cable power presence monitoring 3.3-V and 5-V PCI signaling environments • Separate cable bias (TPBIAS) for each port • Supports PC Card or CardBus with hot • Physical write posting of up to three insertion and removal outstanding transactions • Supports 132-MBps burst transfers to • PCI burst transfers and deep FIFOs to maximize data throughput on both the PCI tolerate large host latency bus and the CardBus • External cycle timer control for customized • Supports serialized IRQ with PCI interrupts synchronization • Programmable multifunction terminals • Extended resume signaling for compatibility • Serial ROM interface for loading subsystem with legacy DV components ID and subsystem vendor ID • PHY-Link logic performs system initialization • ExCA-compatible registers are mapped in and arbitration functions memory or I/O space • PHY-Link encode and decode functions • Intel 82365SL–DF register compatible included for data-strobe bit level encoding • Supports ring indicate, SUSPEND, PCI • PHY-Link incoming data resynchronized to CCLKRUN protocol, and PCI bus lock (LOCK) local clock Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FireWire is a trademark of Apple Computer, Inc.. i.LINK is a trademark of Sony Corporation of America. PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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