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GP4020 Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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GP4020 Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 17 page  10 GP4020 DMA Controller (DMAC) Two DMA engines are available on the microcontroller. These are configured as a pair to provide a memory-to- memory DMA capability between any 2 locations in the ARM7TDMI memory space. They may be used independently for high speed fly-by transfers between UART1 (or UART2) and either on-chip or off-chip locations. Single or multiple byte transfers (Demand or Burst Mode) are supported and may be word, half word or byte wide. Embedded Microcontroller Debug Options The Firefly MF1 Core incorporates three sophisticated methods of hardware and software debug. The options are: q Embedded ICE, accessed via the ARM7TDMI JTAG interface (Multi ICE access also possible) q Angel Debug Monitor q Logic Analyser coupled with an Inverse Assembler, accessed via the SSM debug interface The GP4020 can use any of these options, but special emphasis has been placed on the Embedded ICE and Logic Analyser options. The JTAG and SSM debug interfaces are multiplexed onto the same pins, and can be selected by setting NICE (pin 84) high for SSM, or low for JTAG. Firefly MF1 Microcontroller core The Firefly MF1 Microcontroller is an Embedded Micro- controller core developed by Zarlink Semiconductor. It combines the processing power of the ARM7TDMI microprocessor with a number of peripheral components: • Direct Memory Access Controller (DMAC) • Interrupt Controller (INTC) • Memory Peripheral Controller (MPC), incorporating Up-Integration Module (UIM) • System Services Module (SSM) • System Timer/Counter (SYSTIC) • Universal Asynchronous Receiver / Transmitter (UART) Interrupt Controller (INTC) The ARM7TDMI core accepts two types of interrupt: Normal (IRQ) and Fast (FIQ). All Interrupts can be switched between types, depending upon the relative priorities required. The INTC is the central control logic that decodes the priority level and handles interrupt request signals from a total of 8 fixed pre-defined, internal sources and a number of external sources. General Purpose Input Output (GPIO) This module provides 8 I/O pins, which may be bit or byte addressed and configured in a latched or transparent mode. External Interrupts can be set for edge or level sensitivity with a polarity option. To minimise interrupt latency, there is a hard-wired priority scheme for each channel for both FIQ and IRQ; alternatively this can be ignored and the priority assessment handled in software. Memory/Peripheral Controller (MPC) The MPC ensures the correct multiplexing of data is applied for bus transfers between 8, 16 or 32-bit on-chip or off-chip peripherals. Four different contiguous memory areas are available, each with an address range of 1 MByte, with individually programmable wait and stop state generation. A SWAP function allows memory area 1, which is addressed at system reset, to be switched with memory area 4. This allows, for example, booting from ROM and then switching memory area 1 to address SRAM so that time-critical software and interrupt routines can operate from fast memory. Peripheral Control Logic (PCL) The GP4020 incorporates some specific control logic, which is used to control a number of functions: • System Reset Control • System Power-down, Sleep and Wake-up Control • System Status and Control Registers • Signal input/output multiplex control RAM The GP4020 contains 8KBytes (configured as 2K332-bit) of high-speed (6ns) Static RAM. This can be used for either: • Non-volatile storage of GPS data (Almanac, Ephemeris, Position and Receiver Clock Offset), while the receiver power is disabled • A High-speed Interrupt Service Routine, while the GP4020 is powered up The internal SRAM appears at GP4020 Base Address 0x60000000, served by the MPC Memory Area 4. An MPC SWAP function can swap this memory space with 0x00000000 if required. |
Similar Part No. - GP4020 |
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Similar Description - GP4020 |
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