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SP7653ER Datasheet(PDF) 11 Page - Exar Corporation |
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SP7653ER Datasheet(HTML) 11 Page - Exar Corporation |
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11 / 15 page  Date: /20/06 SP7653 Wide Input Voltage Range, .3MHz, Buck Regulator © Copyright 2006 Sipex Corporation 11 Date: 2/17/06 SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator © Copyright 2006 Sipex Corporation SP765X Thermal Resistance The SP765X family has been tested with a variety of footprint layouts along with different copper area and thermal resistance has been measured. The layouts were done on 4 layer FR4 PCB with the top and bottom layers using 3oz copper and the Power and Ground layers using 1oz copper. For the Minimum footprint, only about 0.1 square inch (of 3 ounces of) copper was used on the top or footprint layer, and this layer had no vias to connect to the 3 other layers. For the Medium footprint, about 0.7 square inches (of 3 ounces of) copper was used on the top layer, but vias were used to connect to the other 3 layers. For the Maximum footprint, about 1.0 square inch (of 3 ounces of) copper was used on the top layer and many vias were used to connect to the 3 other layers. The results show that only about 0.7 square inches (of 3 ounces of) copper on the top layer and vias connecting to the 3 other layers are needed to get the best thermal resistance of 36°C/W. Adding area on the top beyond the 0.7 square inches did not reduce thermal resistance. SP765X Thermal Resistance 4 Layer Board: Top Layer 3ounces Copper GND Layer 1ounce Copper Power Layer 1ounce Copper Bottom Layer 3ounces Copper Minimum Footprint: 44°C/W Top Layer: 0.1 square inch No Vias to other 3 Layers Medium Footprint: 36°C/W Top Layer: 0.7 square inch Vias to other 3 Layers Maximum Footprint: 36°C/W Top Layer: 1.0 square inch Vias to other 3 Layers APPLICATIONS INFORMATION Using a minimum of 0.1 square inches of (3 ounces of) copper on the top layer with no vias connecting to the 3 other layers produced a thermal resistance of 44°C/W. This thermal impedance is only 22% higher than the medium and large footprint layouts, indicating that space constrained designs can still benefit thermally from the Powerblox family of ICs. This indi- cates that a minimum footprint of 0.1 square inch, if used on a 4 layer board, can produce 44°C/W thermal resistance. This approach is still very worthwhile if used in a space con- strained design. The following page shows the footprint layouts from an ORCAD file. The thermal data was taken for still air, not with forced air. If forced air is used, some improvement in thermal resis- tance would be seen. |
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