SN54LV573A, SN74LV573A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCLS411I − APRIL 1998 − REVISED APRIL 2005

2

POST OFFICE BOX 655303

description/ordering information (continued)

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

preventing damaging current backflow through the device when it is powered down.

terminal assignments

1234

A

1D

OE

1Q

B

3D

3Q

2D

2Q

C

5D

4D

5Q

4Q

D

7D

7Q

6D

6Q

E

GND

8D

LE

8Q

FUNCTION TABLE

(each latch)

INPUTS

OUTPUT

OE

LE

D

OUTPUT

Q

L

H

H

H

L

HL

L

L

LX

H

X

X

Z

GQN PACKAGE

(TOP VIEW)

1

234

A

B

C

D

E