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SN74LVCH16244ADGVR Datasheet(PDF) 11 Page - Texas Instruments |
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SN74LVCH16244ADGVR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 26 page 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 1 47 46 44 43 2 3 5 6 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 48 41 40 38 37 8 9 11 12 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 25 36 35 33 32 13 14 16 17 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 24 30 29 27 26 19 20 22 23 Pin numbers shown are for the DGG, DGV, and DL packages. SN74LVCH16244A www.ti.com SCES494B – OCTOBER 2003 – REVISED JUNE 2014 9 Detailed Description 9.1 Overview The SN74LVCH16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. The SN74LVCH16244A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. 9.2 Functional Block Diagram Copyright © 2003–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN74LVCH16244A |
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