SN74LV1T32 datasheet(1/25 Pages) TI1

Part #	SN74LV1T32

Description	Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter

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5 V, 3.3 V, 2.5 V, 1.8 V

1.8 V, 2.5 V, 3.3 V

1.8 V

3.3 V

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SN74LV4T125

SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014

SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State

Output CMOS Logic Level Shifter

1 Features

2 Applications

1

•

Single-Supply Voltage Translator at

•

Tablet

5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC

•

Smartphone

•

Operating Range of 1.8 V to 5.5 V

•

Personal Computer

•

Up Translation

•

Industrial Automotive

–

1.2 V(1) to 1.8 V at 1.8-V VCC

3 Description

–

1.5 V(1) to 2.5 V at 2.5-V VCC

SN74LV4T125 is a low-voltage CMOS buffer gate

–

1.8 V(1) to 3.3 V at 3.3-V VCC

that operates at a wider voltage range for portable,

–

3.3 V to 5.0 V at 5.0-V VCC

telecom, industrial, and automotive applications. The

•

Down Translation

output level is referenced to the supply voltage and is

able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS

–

3.3 V to 1.8 V at 1.8-V VCC

levels.

–

3.3 V to 2.5 V at 2.5-V VCC

The input is designed with a lower threshold circuit to

–

5.0 V to 3.3 V at 3.3-V VCC

match 1.8-V input logic at VCC = 3.3 V and can be

•

Logic Output is Referenced to VCC

used in 1.8 V to 3.3 V level-up translation. In addition,

•

Characterized up to 50 MHz at 3.3-V VCC

the 5-V tolerant input pins enable down translation

(for example, 3.3 V to 2.5 V output at VCC = 2.5 V).

•

5.5 V Tolerance on Input Pins

The wide VCC range of 1.8 V to 5.5 V allows the

•

–40°C to 125°C Operating Temperature Range

generation of desired output levels to connect to

•

Pb-Free Packages Available: SC-70 (RGY)

controllers or processors.

–

3.5 × 3.5 × 1 mm

The SN74LV4T125 device is designed with current-

•

Latch-Up Performance Exceeds 250 mA Per

drive capability of 8 mA to reduce line reflections,

overshoot, and undershoot caused by high-drive

JESD 17

outputs.

•

ESD Performance Tested Per JESD 22

–

2000-V Human-Body Model (A114-B, Class II)

Device Information(1)

–

200-V Machine Model (A115-A)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

–

1000-V Charged-Device Model (C101)

TSSOP (14)

5.00 mm x 4.40 mm

SN74LV4T125

•

Supports Standard Logic Pinouts

VQFN (14)

3.50 mm x 3.50 mm

•

CMOS Output B Compatible with AUP125,

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

LVC125

(1)

Refer the VIH/VIL and output drive for lower VCC condition.

4 Simplified Application Diagram

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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