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SN74LVC112ADBLE Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LVC112ADBLE Datasheet(HTML) 9 Page - Texas Instruments |
9 / 24 page PRE CLK K Q Q CLR J SN74LVC112A www.ti.com SCAS289M – JANUARY 1993 – REVISED DECEMBER 2014 9 Detailed Description 9.1 Overview This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can perform as a toggle flip-flop by tying J and K high. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. 9.2 Functional Block Diagram Figure 4. Logic Diagram, Each Flip-Flop (Positive Logic) 9.3 Feature Description • Wide operating voltage range – Operates from 1.65 V to 3.6 V • Allows down voltage translation – Inputs accept voltages to 5.5 V • Ioff feature – Allows voltages on the inputs and outputs when VCC is 0 V 9.4 Device Functional Modes Table 1. Function Table INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H(1) H(1) H H ↓ L L Q0 Q 0 H H ↓ H L H L H H ↓ L H L H H H ↓ H H Toggle H H H X X Q0 Q0 (1) The output levels in this configuration may not meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Copyright © 1993–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: SN74LVC112A |
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