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SN74LVC244APWRG3 Datasheet(PDF) 11 Page - Texas Instruments

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Part # SN74LVC244APWRG3
Description  SN74LVC244A Octal Buffer or Driver With 3-State Outputs
Download  34 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74LVC244APWRG3 Datasheet(HTML) 11 Page - Texas Instruments

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VCC
Unused Input
Input
Output
Output
Input
Unused Input
–100
–80
–60
–40
–20
0
20
40
60
–1
–0.5 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
VOH – V
VOL – V
–20
0
20
40
60
80
100
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
11
SN74LVC244A
www.ti.com
SCAS414AA – NOVEMBER 1992 – REVISED JUNE 2016
Product Folder Links: SN74LVC244A
Submit Documentation Feedback
Copyright © 1992–2016, Texas Instruments Incorporated
Typical Application (continued)
9.2.3 Application Curves
Figure 5. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
Figure 6. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
10 Power Supply Recommendations
The power supply may be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1 μF capacitor is
recommended for devices with a single supply. If there are multiple VCC terminals, then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is permissible to parallel multiple bypass capacitors to
reject different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies
of noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
11 Layout
11.1 Layout Guidelines
Inputs should not float when using multiple bit logic devices. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples include situations when only two inputs of a triple-input AND
gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected
because the undefined voltages at the outside connections result in undefined operational states.
Specified in the Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally, they will be tied to
GND or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
Figure 7. Layout Diagram


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