0

Output

NINx

PINx

50%

50%

50%

50%

90%

0

Output

10%

NINx

PINx

90%

10%

LM96550

SNAS504F – AUGUST 2010 – REVISED MAY 2013

www.ti.com

Timing Diagrams

RISE AND FALL TIME

The timing diagram shown in Figure 4 defines the rise and fall times tr and tf.

Figure 4. Timing Diagram Defining Rise and Fall Times

tr and tf, respectively

INPUT TO OUTPUT DELAY

The timing diagram shown in Figure 5 defines the delays between the input and output signals.

Figure 5. Timing Diagram Defining Input-to-Output Delays Times

8

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