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LM97600 Datasheet(PDF) 2 Page - Texas Instruments |
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LM97600 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 58 page VREF Clock Management SYNC Control 8-BIT ADC_C VIN3+ VIN3- Data Encoder And Serializer OR Control Logic 8-BIT ADC_D 3 CalRun + - + - S/H S/H VCMO SYNC+ SYNC- Control Inputs Serial Interface VIN4+ VIN4- INPUT MUX 8 8 + + 8-BIT ADC_A 8-BIT ADC_B VIN1+ VIN1- VIN2+ VIN2- + - S/H + + - S/H + CLK+ CLK- Data Bus Output 10 Lanes High Speed Serial Lane 9 Lane 10 Lane 8 Lane 7 Lane 6 Lane 5 Lane 4 Lane 3 Lane 2 Lane 1 8 8 N 2 Rterm Rterm Rterm Rterm Rterm Rterm LM97600 SNAS600A – JULY 2012 – REVISED MARCH 2013 www.ti.com Block Diagram 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM97600 |
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