LM98640

SNAS596A – JUNE 2012 – REVISED MAY 2013

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PIN DESCRIPTIONS (continued)

Pin

Name

Typ

Res

Description

46

TXOUT0-

O

D

LVDS Data Out0-

47

TXCLK+

O

D

LVDS Clock+

48

TXCLK-

O

D

LVDS Clock-

49

VSS18

P

Digital supply return.

50

VDD18

P

Digital power supply. Decouple with minimum 0.1 µF capacitor to VSS18 plane.

51

ATB0

O

A

Analog Test Bus. If not used, can be connected to VSS18 through a 10 k

Ω resistor.

52

ATB1

O

A

Analog Test Bus. If not used, can be connected to VSS18 through a 10 k

Ω resistor.

53

VDD18

P

Digital power supply. Decouple with minimum 0.1 µF capacitor to VSS18 plane.

54

VDD18

P

Digital power supply. Decouple with minimum 0.1 µF capacitor to VSS18 plane.

55

VSS18

P

Digital supply return.

56

VSS18

P

Digital supply return.

57

INCLK-

I

D

Clock Input. Inverting input for LVDS clocks.

58

INCLK+

I

D

Clock Input. Non-Inverting input for LVDS clocks.

59

VSS33

P

Analog supply return.

60

VDD33

P

Analog power supply. Decouple with minimum 0.1 µF capacitor to VSS33 plane.

61

VDD33

P

Analog power supply. Decouple with minimum 0.1 µF capacitor to VSS33 plane.

62

VSS33

P

Analog supply return.

63

IBIAS0

I

A

Connect with external 10 k

Ω 1% resistor to IBIAS1 pin.

64

IBIAS1

I

A

Connect with external 10 k

Ω 1% resistor to IBIAS0 pin.

65

VREFBG

O

A

Band gap reference output. Bypass with a 0.1 µF capacitor to VSS33. Can be overdriven

with external voltage source.

66

VSS33

P

Analog supply return.

67

VREFT1

O

A

Top of ADC reference. Bypass with a 0.1 µF capacitor to VSS33.

68

VREFB1

O

A

Bottom of ADC reference. Bypass with a 0.1 µF capacitor to VSS33.

Exp Pad

P

Exposed pad must be soldered to ground plane to ensure rated performance.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

6

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