SN75ALS162

OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER

SLLS020C – JUNE 1986 – REVISED MAY 1995

6

POST OFFICE BOX 655303

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST

CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH

Propagation delay time,

low- to high-level output

Terminal

Bus

CL = 30 pF,

10

20

ns

tPHL

Propagation delay time,

high- to low-level output

Terminal

Bus

L

See Figure 1

12

20

ns

tPLH

Propagation delay time,

low- to high-level output

Bus

Terminal

CL = 30 pF,

5

10

ns

tPHL

Propagation delay time,

high- to low-level output

Bus

Terminal

L

,

See Figure 2

7

14

ns

tPZH

Output enable time to high level

Bus

30

tPHZ

Output disable time from high level

TE DC or SC

Bus

(ATN, EOI,

CL = 15 pF,

20

ns

tPZL

Output enable time to low level

TE, DC, or SC

(,

,

REN, IFC,

dDAV)

L

,

See Figure 3

45

ns

tPLZ

Output disable time from low level

and DAV)

20

tPZH

Output enable time to high level

30

tPHZ

Output disable time from high level

TE DC or SC

Terminal

CL = 15 pF,

25

ns

tPZL

Output enable time to low level

TE, DC, or SC

Terminal

L

See Figure 4

30

ns

tPLZ

Output disable time from low level

25

† All typical values are at TA = 25°C.

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT

VOLTAGE WAVEFORMS

VOL

VOH

0 V

3 V

1.0 V

1.5 V

See Note B

2.2 V

1.5 V

Bus

Output

Terminal

Input

Test Point

CL =30 pF

(see Note A)

480

Ω

200

Ω

From (bus)

Output Under

Test

5 V

tPLH

tPHL

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR

≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO

= 50

Ω.

Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms