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P4C1024-15J4C Datasheet(PDF) 4 Page - Pyramid Semiconductor Corporation |
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P4C1024-15J4C Datasheet(HTML) 4 Page - Pyramid Semiconductor Corporation |
4 / 8 page P4C1024 Page 4 of 14 Document # SRAM124 REV A AC ELECTRICAL CHARACTERISTICS—READ CYCLE (V CC = 5V ± 10%, All Temperature Ranges) (2) Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max tRC Read Cycle Time 15 20 25 35 45 55 70 85 100 120 ns tAA Address Access Time 15 20 25 35 45 55 70 85 100 120 ns tAC Chip Enable Access Time 15 20 25 35 45 55 70 85 100 120 ns tOH Output Hold from Address Change 333333333 3 ns tLZ Chip Enable to Output in Low Z 333333333 3 ns tHZ Chip Disable to Output in High Z 8 9 11 15 20 25 30 35 40 50 ns tOE Output Enable Low to Data Valid 7 9 11 15 20 25 30 35 40 50 ns tOLZ Output Enable Low to Low Z 000000000 0 ns tOHZ Output Enable High to High Z 7 9 11 15 20 25 30 35 40 50 ns tPU Chip Enable to Power Up Time 000000000 0 ns tPD Chip Disable to Power Down Time 12 20 20 20 25 30 35 40 45 50 ns Symbol Parameter -15 -20 -25 -35 -45 Unit -55 -70 -85 -100 -120 Notes: 5. WE is HIGH for READ cycle. 6. CE 1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE 1 transition LOW and CE 2 transition HIGH. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. TIMING WAVEFORM OF READ CYCLE NO. 1 (OE OE OE OE OE CONTROLLED)(5) |
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